Spread spectrum block control apparatus and spread spectrum clock generating apparatus

• US 7,885,353 B2
• Filed: 03/02/2007
• Issued: 02/08/2011
• Est. Priority Date: 03/03/2006
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Nakadaira, Masao
• Primary Examiner(s): Payne; David C
• Assistant Examiner(s): Perez; James M
• Application Number:
  US11/712,977
• Publication Number:
  US 20070206659A1
• Time in Patent Office: 1,439 Days
• Field of Search: 375/354, 375/371, 375/373, 375/37, 375/295, 375/302, 375/303, 375/374, 327/100, 327/141, 327/144, 327/151, 327/291, 327/298, 327/114
• US Class Current: 375/303
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
• CPC Class Codes: H04B 2215/064 Reduction of clock or synthesizer reference frequency harmonics
• CPC Class Codes: H04B 2215/067 by modulation dispersion

Abstract

Disclosed is an SSC controller that exercises control to supply a control signal to a phase interpolator which receives an input clock signal and varies the phase of an output clock signal in accordance with the control signal, and to frequency-modulate the output clock signal. In an SSC controller, a counting operation control circuit outputs a counting operation control signal that controls count enable and disable. A p-counter receives a frequency-divided clock signal from a frequency divider and counts the signal when the counting operation control signal from the counting operation control circuit indicates count enable. Upon counting up to a predetermined first value, the counting operation control circuit generates a first output signal and sets its count value to zero. When the counting operation control signal indicates count disable, the p-counter stops counting. An up/down counter receives the first output signal from the p-counter and counts this signal up and down between a predetermined initial value (=0) and a predetermined second value. On the basis of count values from the two counters, a controller outputs the phase control signal to the phase interpolator. The counting operation control circuit, which receives the count values from the two counters and is supplied with a control signal from an SSC control terminal, sets the counting operation control signal to a value indicative of count disable when the supplied control signal indicates count disable and both of the count values from the two counters are at their initial values (=0).

Claims

1. A spread spectrum clock control apparatus for exercising control to supply a phase control signal to a phase interpolator that receives an input clock signal and varies the phase of an output clock signal thereof in accordance with the phase control signal, and to frequency-modulate the output clock signal of said phase interpolator, said apparatus comprising;

a counter that receives the input clock signal and counts the input clock signal;

a circuit that generates the phase control signal based upon result of the count; and

a counting operation control circuit that receives a control signal, which is for turning an SSC (Spread Spectrum Clock) function ON and OFF, and exercises control so as to enable the counting operation by the counter if the control signal indicates SSC-function ON, and disable the counting operation of the counter at the moment a count value in the counter reaches a predetermined value when the control signal has become a value indicating SSC-function OFF,

wherein said counting operation control circuit performs control for halting supply of the clock signal to the counter at the moment the count value in the counter reaches a predetermined value when the control signal has become the value indicating SSC-function OFF.

2. The apparatus according to claim 1, wherein the phase control signal includes a down signal that retards the phase of the output clock signal.

3. The apparatus according to claim 1, wherein the phase control signal includes a down signal that retards the phase of the output clock signal and/or an up signal that advances the phase of the output clock signal.

4. A spread spectrum clock generating apparatus comprising the spread spectrum control clock apparatus according to claim 1, and further comprising:

a phase interpolator receiving an input clock signal and varying the phase of an output clock signal in accordance with a phase control signal, wherein the spread spectrum clock control apparatus is for exercising control to supply the phase control signal to said phase interpolator and to frequency-modulate the output clock signal.

5. A spread spectrum clock control apparatus for exercising control to supply a phase control signal to a phase interpolator that receives an input clock signal and varies the phase of an output clock signal thereof in accordance with the phase control signal, and to frequency-modulate the output clock signal of said phase interpolator, said apparatus comprising:

a counting operation control circuit that outputs a counting operation control signal for controlling count enable and disable;

a first counter that, when the counting operation control signal from said counting operation control circuit indicates count enable, receives and counts the input clock signal and, when the signal has been counted up to a predetermined first value, outputs a first output signal and sets the count of the counter to an initial value, and that, when the counting operation control signal indicates count disable, halts the counting operation;

a second counter that receives the first output signal from said first counter, and counts the first output signal up and down between a predetermined initial value and a predetermined second value; and

a controller that outputs the phase control signal to said phase interpolator based upon count values from said first and second counters;

wherein the counting operation control circuit receives a control signal for on/off controlling an SSC (spread spectrum clock) function as well as the count values from said first and second counters, sets the counting operation control signal to a value indicating count disable, when the control signal indicates SSC-function OFF and when both of the count values from said first and second counters are initial values, and sets the counting operation control signal to a value indicating count enable at all other times.

6. The apparatus according to claim 5, further comprising a frequency divider circuit that receives the input clock signal, said frequency divider circuit being arranged in front of said first counter and supplying a frequency-divided clock signal to said first counter.

7. The apparatus according to claim 6, wherein said controller receives the frequency-divided clock from said frequency divider circuit and the count values from said first and second counters as inputs, and outputs the phase control signal to said phase interpolator based upon the count values from said first and second counters at a timing stipulated by the frequency-divided clock.

8. The apparatus according to claim 5, wherein the phase control signal includes a down signal that retards the phase of the output clock signal.

9. The apparatus according to claim 5, wherein the phase control signal includes a down signal that retards the phase of the output clock signal and/or an up signal that advances the phase of the output clock signal.

10. A spread spectrum clock generating apparatus comprising the spread spectrum control clock apparatus according to claim 5, and further comprising:

a phase interpolator receiving an input clock signal and varying the phase of an output clock signal in accordance with a phase control signal, wherein the spread spectrum clock control apparatus is for exercising control to supply the phase control signal to said phase interpolator and to frequency-modulate the output clock signal.

11. A spread spectrum clock control apparatus for exercising control to supply a phase control signal to a phase interpolator which receives an input clock signal and varies the phase of an output clock signal thereof in accordance with the phase control signal, and to frequency-modulate the output clock signal of said phase interpolator, said apparatus comprising:

a first counter that receives and counts the input clock signal and, when the signal has been counted up to a predetermined first value, outputs a first output signal and sets the count to an initial value;

a second counter that receives the first output signal from said first counter, and counts the first output signal up and down between a predetermined initial value and a predetermined second value;

a controller that outputs the phase control signal to said phase interpolator based upon count values from said first and second counters; and

a clock control circuit that controls supply and halting of the clock signal to said first counter;

wherein said clock control circuit receives a control signal for on/off controlling an SSC (spread spectrum clock) function as well as the count values from said first and second counters, and exercises control so as to halt supply of the clock signal to said first counter, when the control signal indicates SSC-function OFF and when both of the count values from said first and second counters are initial values, and to supply the clock signal to said first counter at all other times.

12. The apparatus according to claim 11, further comprising a frequency divider circuit that receives the input clock signal, said frequency divider circuit being arranged in front of said clock control circuit and supplying a frequency-divided clock signal to said clock control circuit;

said clock control circuit halting supply of the frequency-divided clock signal to said first counter when the control signal indicates SSC-function OFF and, moreover, both of the count values from said first and second counters are initial values, and supplying the frequency-divided clock signal to said first counter at all other times.

13. The apparatus according to claim 12, wherein said controller receives the frequency-divided clock from said frequency divider circuit and the count values from said first and second counters as inputs, and outputs the phase control signal to said phase interpolator based upon the count values from said first and second counters at a timing stipulated by the frequency-divided clock.

14. The apparatus according to claim 11, wherein the phase control signal includes a down signal that retards the phase of the output clock signal.

15. The apparatus according to claim 11, wherein the phase control signal includes a down signal that retards the phase of the output clock signal and/or an up signal that advances the phase of the output clock signal.

16. A spread spectrum clock generating apparatus comprising the spread spectrum control clock apparatus according to claim 11, and further comprising:

a phase interpolator receiving an input clock signal and varying the phase of an output clock signal in accordance with a phase control signal, wherein the spread spectrum clock control apparatus is for exercising control to supply the phase control signal to said phase interpolator and to frequency-modulate the output clock signal.