Multi-gigabit per second concurrent encryption in block cipher modes
First Claim
1. A system adapted to encrypt one or more packets of plaintext data in CBC mode, comprising:
- a plurality of digital logic components connected in series, respective components operative to process one or more rounds of a block cipher algorithm, wherein the plurality of digital logic components are configured to concurrently process different blocks of data that correspond to different plaintext packets with the one or more rounds of the block cipher algorithm;
a plurality of N bit registers, N being a positive integer, respective registers interleaved between respective logic components;
an XOR component that receives blocks of plaintext data and blocks of ciphertext data, the XOR component XORing blocks of plaintext data for respective plaintext packets with previously encrypted blocks of ciphertext data for those plaintext packets, the XOR component iteratively feeding the XOR'"'"'d blocks of data into a first of the plurality of the digital logic components, wherein the blocks of plaintext data are distinguishable from an initialization vector;
a circuit component operative to selectively pass blocks of ciphertext data fed back from an output of a final logic component to the XOR component;
a data select component that facilitates selective application of blocks of plaintext data to the XOR component; and
a clock operatively coupled to respective N bit registers, the circuit component, the key select component and the data select component, the clock adapted to provide a signal to which keys and packets of data are selectively concurrently advanced into and through the system.
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Abstract
One embodiment is a system adapted to encrypt one or more packets of plaintext data in cipher-block chaining (CBC) mode. The system includes a plurality of digital logic components connected in series, where respective components are operative to process one or more rounds of a block cipher algorithm. A plurality of N bit registers are respectively coupled to the plurality of digital logic components. An XOR component receives blocks of plaintext data and blocks of ciphertext data, and XORs blocks of plaintext data for respective plaintext packets with previously encrypted blocks of ciphertext data for those plaintext packets. The XOR component iteratively feeds the XOR'"'"'d blocks of data into a first of the plurality of the digital logic components. In addition, a circuit component is operative to selectively pass blocks of ciphertext data fed back from an output of a final logic component to the XOR component.
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Citations
15 Claims
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1. A system adapted to encrypt one or more packets of plaintext data in CBC mode, comprising:
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a plurality of digital logic components connected in series, respective components operative to process one or more rounds of a block cipher algorithm, wherein the plurality of digital logic components are configured to concurrently process different blocks of data that correspond to different plaintext packets with the one or more rounds of the block cipher algorithm; a plurality of N bit registers, N being a positive integer, respective registers interleaved between respective logic components; an XOR component that receives blocks of plaintext data and blocks of ciphertext data, the XOR component XORing blocks of plaintext data for respective plaintext packets with previously encrypted blocks of ciphertext data for those plaintext packets, the XOR component iteratively feeding the XOR'"'"'d blocks of data into a first of the plurality of the digital logic components, wherein the blocks of plaintext data are distinguishable from an initialization vector; a circuit component operative to selectively pass blocks of ciphertext data fed back from an output of a final logic component to the XOR component; a data select component that facilitates selective application of blocks of plaintext data to the XOR component; and a clock operatively coupled to respective N bit registers, the circuit component, the key select component and the data select component, the clock adapted to provide a signal to which keys and packets of data are selectively concurrently advanced into and through the system. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification