Methods and systems of managing memory addresses in a large capacity multi-level cell (MLC) based flash memory device

• US 7,886,108 B2
• Filed: 02/04/2008
• Issued: 02/08/2011
• Est. Priority Date: 01/06/2000
• Status: Expired due to Fees

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Nguyen, David, Shen, Ming-Shiang, Lee, Charles C., Ma, Abraham Chih-Kang, Yu, I-Kang
• Primary Examiner(s): Shah; Sanjiv
• Assistant Examiner(s): YU, JAE UN
• Application Number:
  US12/025,706
• Publication Number:
  US 20080256287A1
• Time in Patent Office: 1,100 Days
• Field of Search: 711/103, 711/203, 711/206
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.

Claims

1. A method of managing memory address of a multi-level cell (MLC) based flash memory device comprising:

receiving, in the MLC based flash memory device, a logical sector address (LSA) along with a data transfer request from a host computing device;

extracting set, entry, page and sector numbers from the LSA with an indexing scheme;

loading a set, corresponding to the set number, of partial logical-to-physical address and page usage information (PLTPPUI) into an address correlation page usage memory (ACPUM);

reading a physical block number of flash memory of the MLC based flash memory device, the physical block number corresponds to the entry number in the ACPUM; and

when the data transfer request is a read request, reading data from a physical page corresponding to the page number to a page buffer, and sending a requested data sector from the page buffer in accordance with the sector number received from the host computing device;

when the data transfer request is a write request, writing page buffer contents to a physical page corresponding to the page number if the page buffer contents have been modified, writing a received data sector to the page buffer in accordance with the sector number received from the host computing device and setting corresponding one of a plurality of sector update flags reflecting the data sector just written into the page buffer.

2. The method of claim 1, further comprises writing ACPUM contents to one of a plurality of first physical blocks in a reserved area of the flash memory, if the ACPUM contents have been modified, before loading the set of PLTPPUI into the ACPUM.

3. The method of claim 2, wherein the ACPUM contents are written to, said one of the first physical blocks one page at a time based on a set of MLC data programming rules which includes:

(a) writing to a higher page number sequentially in a same one of the first physical blocks, and (b) since each page can only be written once thereby requiring a new blank one of the first physical blocks for writing to an already modified page.

4. The method of claim 3, wherein each of the first physical blocks in the reserved area is referenced by one of a plurality of first special logical addresses and a correlation between the first physical blocks and the first special logical addresses is kept in a PLTPPUI tracking table.

5. The method of claim 4, wherein the PLTPPUI tracking table further contains a tracking number and a highest page number for said each of the first physical blocks, the tracking number is configured for identifying which version of a particular set of PLTPPUI is stored in said each of the first physical blocks and the highest page is configured for tracking which page has been written in said each of the first physical blocks.

6. The method of claim 5, wherein the tracking number associated with particular one of the first special logical addresses are written to spare area of first page of said each of the first physical blocks in the reserved area of the flash memory.

7. The method of claim 6, wherein the PLTPPUI tracking table is rebuilt in each initialization of the MLC flash memory device from stored tracking number and stored first special logical address in the spare area of the first page of said each of the first physical blocks in the reserved area of the flash memory.

8. The method of claim 5, further comprises writing wear leveling counter and bad block indicator (WL/BB) of the flash memory into a plurality of second physical blocks that is referenced by a plurality of second special logical addresses.

9. The method of claim 8, wherein correlation of the second physical blocks and the second special addresses is kept in a WL/BB tracking table.

10. The method of claim 2, wherein the reserved area of the flash memory is defined in an initial manufacturing program by the manufacturer of the MLC based flash memory device.

11. The method of claim 2, further comprises writing the modified page buffer contents and the modified ACPUM contents to the flash memory if the MLC based flash memory device has been idling for more than a predefined period of time.

12. The method of claim 2, further comprises performing background recycling of physical blocks containing stale data.

13. The method of claim 1, wherein the indexing scheme comprises the PLTPPUI and is based on physical characteristics of the flash memory including total number of sets, entries, pages and sectors, and ratios among said sets, said entries, said pages and said sectors.

14. A multi-level cell (MLC) based flash memory device adapted to be accessed by a host computing device comprising:

an upper housing structure;

a lower housing structure; and

a core unit enclosed in between the upper and lower housing structures, wherein the core unit comprises an interface connector and a print circuit board with at least one MLC based flash memory chip and a flash memory controller mounted thereon,

wherein the flash memory controller is configured for managing memory address of the flash memory device with following operations;

receiving, in the MLC based flash memory device, a logical sector address (LSA) along with a data transfer request from a host computing device;

extracting set, entry, page and sector numbers from the LSA with an indexing scheme;

loading a set, corresponding to the set number, of partial logical-to-physical address and page usage information (PLTPPUI) into an address correlation page usage memory (ACPUM);

reading a physical block number of flash memory of the MLC based flash memory device, the physical block number corresponds to the entry number in the ACPUM; and

when the data transfer request is a read request, reading data from a physical page corresponding to the page number to a page buffer, and sending a requested data sector from the page buffer in accordance with the sector number received from the host computing device;

when the data transfer request is a write request, writing page buffer contents to the physical page corresponding to the page number of if the page buffer contents have been modified, writing a received data sector to the page buffer in accordance with the sector number received from the host computing device and setting corresponding one of a plurality of sector update flags reflecting the data sector just written into the page buffer.

15. The flash memory device of claim 14 further comprises a fingerprint sensor adapted to scan a fingerprint of a user of the flash memory device and to generate fingerprint scan data, wherein the generated fingerprint scan data is compared with fingerprint reference data to authenticate the user.

16. The flash memory device of claim 14 further comprises a layer of conforming coating configured for preventing oxidation of integrated circuit leads or soldering area;

covering or protecting extreme temperature exposure either cold or hot; and

waterproofing for certain military or industrial applications.

17. The flash memory device of claim 14, wherein said interface connector includes an interface circuit of one of Universal Serial Bus (USB), Secure Digital (SD), Micro SD, Multi-Media Card (MMC), Compact Flash (CF), Memory Stick (MS), PCI-Express, a Integrated Drive Electronics (IDE), Serial Advanced Technology Attachment (SATA), external SATA, Radio Frequency Identification (RFID), fiber channel and optical connection.