Driving values to DC adjusted/untimed nets to identify timing problems
First Claim
1. A computer program product comprising a computer useable storage device having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to:
- receive an integrated circuit design;
receive a “
don'"'"'t care”
(DC) adjusted list that identifies net segments that do not need to adhere to timing requirements;
compare entries in the DC adjusted list to a netlist for the integrated circuit design to identify an untimed net segment based on a match of a net segment in the DC adjusted list with a net in the netlist for the integrated circuit design;
drive a value along a pathway to the at least one untimed net segment;
monitor an output state value from the untimed net segment;
verify an operation of the untimed net segment of the integrated circuit design based on the collected output value from the untimed net segment;
determine whether there is a violation in the operation of the untimed net segment;
determine whether downstream logic in the integrated circuit design uses the output value; and
remove the untimed net segment from the DC adjusted list if there is a violation in the operation of the untimed net segment and downstream logic in the integrated circuit design does not use the output value.
5 Assignments
0 Petitions
Accused Products
Abstract
An apparatus and computer program product for driving values to “don'"'"'t care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The apparatus and computer program product may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the apparatus and computer program product, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the apparatus and computer program product may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.
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Citations
20 Claims
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1. A computer program product comprising a computer useable storage device having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to:
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receive an integrated circuit design; receive a “
don'"'"'t care”
(DC) adjusted list that identifies net segments that do not need to adhere to timing requirements;compare entries in the DC adjusted list to a netlist for the integrated circuit design to identify an untimed net segment based on a match of a net segment in the DC adjusted list with a net in the netlist for the integrated circuit design; drive a value along a pathway to the at least one untimed net segment; monitor an output state value from the untimed net segment; verify an operation of the untimed net segment of the integrated circuit design based on the collected output value from the untimed net segment; determine whether there is a violation in the operation of the untimed net segment; determine whether downstream logic in the integrated circuit design uses the output value; and remove the untimed net segment from the DC adjusted list if there is a violation in the operation of the untimed net segment and downstream logic in the integrated circuit design does not use the output value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An apparatus, comprising:
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a processor; and a memory coupled to the processor, wherein the memory contains instructions which, when executed by the processor, cause the processor to; receive an integrated circuit design; receive a “
don'"'"'t care”
(DC) adjusted list that identifies net segments that do not need to adhere to timing requirements;compare entries in the DC adjusted list to a netlist for the integrated circuit design to identify an untimed net segment based on a match of a net segment in the DC adjusted list with a net in the netlist for the integrated circuit design; drive a value along a pathway to the at least one untimed net segment; monitor an output state value from the untimed net segment; verify an operation of the untimed net segment of the integrated circuit design based on the collected output value from the untimed net segment; determine whether there is a violation in the operation of the untimed net segment; determine whether downstream logic in the integrated circuit design uses the output value; and remove the untimed net segment from the DC adjusted list if there is a violation in the operation of the untimed net segment and downstream logic in the integrated circuit design does not use the output value. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A computer program product comprising a computer useable storage device having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to:
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receive the integrated circuit design; receive a “
don'"'"'t care”
(DC) adjusted list that identifies net segments that do not need to adhere to timing requirements;compare entries in the DC adjusted list to a netlist for the integrated circuit design to identify an untimed net segment based on a match of a net segment in the DC adjusted list with a net in the netlist for the integrated circuit design; convert the untimed net segment to single source and single sink net; identify a source latch that feeds the untimed net segment; identify, in the integrated circuit design, a path to the untimed net segment from its source latch; replicate, in the integrated circuit design, the identified path to form a replicated path; drive a value to the untimed net segment along the identified path and the replicated path; monitor an output state value from the untimed net segment; and verify an operation of the untimed net segment of the integrated circuit design based on the collected output value from the untimed net segment; determine whether there is a violation in the operation of the untimed net segment; determine whether downstream logic in the integrated circuit design uses the output value; and remove the untimed net segment from the DC adjusted list if there is a violation in the operation of the untimed net segment and downstream logic in the integrated circuit design does not use the output value. - View Dependent Claims (17, 18, 19, 20)
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Specification