Method of making a pillar pattern using triple or quadruple exposure

• US 7,887,999 B2
• Filed: 12/27/2007
• Issued: 02/15/2011
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Petti, Christopher J.
• Primary Examiner(s): CHACKO DAVIS, DABORAH
• Application Number:
  US12/005,276
• Publication Number:
  US 20090170030A1
• Time in Patent Office: 1,146 Days
• Field of Search: None
• US Class Current: 430/394
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G03F 7/203 comprising an imagewise exposure to electromagnetic radiation or corpuscular radiation
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: Y10S 430/153 Multiple image producing on single receiver

Abstract

Methods of making pillar shaped device array using a triple or quadruple exposure technique are described. A plurality of pillar shaped devices are formed arranged in a hexagonal or rectangular pattern.

Claims

1. A method of making a device, comprising:

forming a photoresist layer over a substrate;

performing a first exposure of the photoresist layer using a first mask to form first exposed regions in the photoresist layer;

performing a second exposure of the photoresist layer using a second mask to form second exposed regions in the photoresist layer;

performing a third exposure of the photoresist layer using a third mask to form third exposed regions in the photoresist layer, such that each adjacent first, second and third exposed regions are approximately equidistant from each other;

patterning the photoresist layer after the first, the second and the third exposures;

etching the substrate using the patterned photoresist layer;

forming a plurality of pillar shaped devices arranged in a substantially hexagonal pattern, wherein the substantially hexagonal pattern comprises a repeating pattern of seven nonvolatile memory cells having a central nonvolatile memory cell surrounded by six other nonvolatile memory cells arranged in a hexagonal layout around the central nonvolatile memory cell;

forming a plurality of bit lines using double photoresist exposure; and

and forming a plurality of word lines using double photoresist exposure.

2. The method of claim 1, wherein the step of etching the substrate comprises etching a hard mask layer located below the photoresist layer followed by etching at least one semiconductor layer located below the hard mask layer to form the pillar shaped nonvolatile memory cells.

3. The method of claim 1, wherein the photoresist layer is a negative photoresist.

4. The method of claim 1, wherein the photoresist layer is a positive photoresist.

5. The method of claim 4, wherein:

the step of patterning the photoresist layer after the first, the second and the third exposures comprises forming holes in the positive photoresist layer; and

the step of etching the substrate using the patterned photoresist layer comprises forming a hard mask layer in the holes in the positive photoresist layer, removing the photoresist layer, and etching at least one semiconductor layer located below the hard mask layer to form the pillar shaped nonvolatile memory cells.

6. The method of claim 1, wherein the plurality of bit lines and the plurality of word lines are located in two different planes, and the plurality of word lines cross the plurality of bit lines at an angle of about 60 degrees.

7. The method of claim 1, wherein each nonvolatile memory cell comprises a one time programmable or a rewritable cell selected from at least one of antifuse, fuse, diode and antifuse arranged in a series, polysilicon memory effect cell, metal oxide memory, switchable complex metal oxide, carbon nanotube memory, graphene switchable resistance material, phase change material memory, conductive bridge element, or switchable polymer memory.

8. The method of claim 1, wherein at least two of the first, the second and the third masks comprise a same mask.

9. The method of claim 1, wherein the plurality of pillar shaped devices comprise magnetic storage material.

10. A method of making a device, comprising:

forming at least one semiconductor layer over first conductor lines;

forming a first photoresist layer over the at least one semiconductor layer;

performing a first exposure of the first photoresist layer using a first mask to form first exposed regions in the first photoresist layer;

performing a second exposure of the first photoresist layer using a second mask to form second exposed regions in the first photoresist layer;

performing a third exposure of the first photoresist layer using a third mask to form third exposed regions in the first photoresist layer;

performing a fourth exposure of the first photoresist layer using a fourth mask to form fourth exposed regions in the first photoresist layer;

patterning the first photoresist layer after the first, the second, the third and the fourth exposures;

etching the at least one semiconductor layer to form a plurality of pillar shaped devices; and

forming a plurality of second conductor lines over the plurality of pillar shaped devices,

wherein the first conductor lines comprise word lines, the second conductor lines comprise bit lines, and the pillar shaped devices comprise nonvolatile memory cells arranged in a square or rectangular pattern.

11. A method of making a device, comprising:

forming a first photoresist layer over at least one first conductive layer located over a substrate;

performing a first exposure of the first photoresist layer using a first mask to form first exposed regions in the first photoresist layer;

performing a second exposure of the first photoresist layer using a second mask to form second exposed regions in the first photoresist layer;

patterning the first photoresist layer after the first and the second exposures;

etching the at least one first conductive layer using the patterned first photoresist layer as a mask to form a plurality of first conductor lines;

forming at least one semiconductor layer over the plurality of first conductor lines;

forming a second photoresist layer over the at least one semiconductor layer;

performing a third exposure of the second photoresist layer using a third mask to form third exposed regions in the second photoresist layer;

performing a fourth exposure of the second photoresist layer using a fourth mask to form fourth exposed regions in the second photoresist layer;

performing a fifth exposure of the second photoresist layer using a fifth mask to form fifth exposed regions in the second photoresist layer;

performing a sixth exposure of the second photoresist layer using a sixth mask to form sixth exposed regions in the second photoresist layer;

patterning the second photoresist layer after the third, the fourth, the fifth and the sixth exposures;

etching the at least one semiconductor layer to form a plurality of pillar shaped devices; and

forming a plurality of second conductor lines over the plurality of pillar shaped devices.

12. A method of making a device, comprising:

forming at least one semiconductor layer over first conductor lines formed from at least one first conductive layer;

forming a first photoresist layer over the at least one semiconductor layer;

performing a first exposure of the first photoresist layer using a first mask to form first exposed regions in the first photoresist layer;

performing a second exposure of the first photoresist layer using a second mask to form second exposed regions in the first photoresist layer;

performing a third exposure of the first photoresist layer using a third mask to form third exposed regions in the first photoresist layer;

performing a fourth exposure of the first photoresist layer using a fourth mask to form fourth exposed regions in the first photoresist layer;

patterning the first photoresist layer after the first, the second, the third and the fourth exposures;

etching the at least one semiconductor layer to form a plurality of pillar shaped devices;

forming at least one second conductive layer over the pillar shaped devices;

forming a second photoresist layer over the at least one second conductive layer;

performing a fifth exposure of the second photoresist layer using a fifth mask to form fifth exposed regions in the second photoresist layer;

performing a sixth exposure of the second photoresist layer using a sixth mask to form sixth exposed regions in the second photoresist layer;

patterning the second photoresist layer after the fifth and the sixth exposures; and

etching the at least one second conductive layer using the patterned second photoresist layer as a mask to form a plurality of second conductor lines.

13. The method of claim 12, wherein the first conductor lines comprise word lines, the second conductor lines comprise bit lines, and the pillar shaped devices comprise nonvolatile memory cells arranged in a square or a rectangular pattern.

14. The method of claim 12, further comprising:

forming a third photoresist layer over the at least one first conductive layer located over a substrate;

performing a seventh exposure of the third photoresist layer using a seventh mask to form seventh exposed regions in the third photoresist layer;

performing a eighth exposure of the third photoresist layer using a eighth mask to form eighth exposed regions in the third photoresist layer;

patterning the third photoresist layer after the seventh and the eighth exposures; and

etching the at least one first conductive layer using the patterned third photoresist layer as a mask to form a plurality of the first conductor lines.