Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors

• US 7,888,201 B2
• Filed: 04/25/2007
• Issued: 02/15/2011
• Est. Priority Date: 11/04/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeo, Yee-Chia, Yang, Fu-Liang, Hu, Chenming
• Primary Examiner(s): Monbleau; Davienne
• Assistant Examiner(s): Trinh; Hoa B
• Application Number:
  US11/789,616
• Publication Number:
  US 20070264762A1
• Time in Patent Office: 1,392 Days
• Field of Search: 438/151, 438/164, 438/238, 257/E21.661
• US Class Current: 438/238
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A static memory element includes a first inverter having an input coupled to a left bit node and an output coupled to a right bit node. A second inverter has an input coupled to the right bit node and an output coupled to the left right bit node. A first fully depleted semiconductor-on-insulator transistor has a drain coupled to the left bit node, and a second fully depleted semiconductor-on-insulator transistor has a drain coupled to the right bit node.

Claims

1. A method of forming a SRAM cell, the method comprising:

providing a silicon-on-insulator substrate, said substrate comprising a silicon layer overlying an insulator layer;

defining at least one active region in the silicon layer;

forming a gate dielectric layer in the active region;

forming a plurality of gate electrodes overlying the gate dielectric layer; and

forming source and drain regions adjacent to the plurality of gate electrodes to form a fully depleted transistor and a partially depleted transistor as two transistors of the SRAM cell, wherein the fully depleted transistor has a greater channel length than the partially depleted transistor.

2. The method of claim 1 wherein the fully depleted transistor is a pass-gate transistor of the SRAM cell.

3. The method of claim 1 wherein the partially depleted transistor is a pull-down or a pull-up transistor of the SRAM cell.

4. The method of claim 1 further comprising a step of forming a high-stress film covering the gate electrode, source region, and drain region of at least one of the fully depleted transistor or the partially depleted transistor.

5. The method of claim 4 wherein the high stress film contacts a sidewall surface of the active region.

6. The method of claim 1 and further comprising, after forming the gate electrode, forming source and drain extension regions.

7. The method of claim 6 and further comprising, after forming the source and drain extension regions, forming super halo region.

8. The method of claim 7 wherein the super halo region is formed by ion implantation.

9. The method of claim 8 wherein the super halo region has a doping concentration in the range of about 1×

10¹⁸ to about 2×

10¹⁹ cm<sup>−

3</sup>.

10. The method of claim 1 wherein the silicon layer has a thickness in the range of about 10 angstroms to about 2000 angstroms.

11. The method of claim 1 wherein the silicon layer has a thickness of less than about 200 angstroms.

12. The method of claim 1 wherein the active regions have rounded corners.

13. The method of claim 12 wherein at least one of the rounded corners has a radius of about 10 angstroms to about 200 angstroms.

14. A method of forming a SRAM cell, the method comprising:

providing a silicon-on-insulator substrate, said substrate comprising a silicon layer overlying an insulator layer;

forming one or more active regions within the substrate, at least one of the one or more active regions having a first section with a first width and a second section with a second width, the first width being different than the second width;

forming a fully depleted pass-gate transistor by a method comprising;

forming a gate dielectric layer over the one or more active regions;

forming a gate electrode layer over the gate dielectric layer;

patterning the gate electrode layer to form a first gate electrode in the first section of the at least one of the one or more active regions, wherein the first gate electrode has a first gate length; and

forming first source and drain regions of opposing sides of the first gate electrode; and

forming a partially depleted transistor by a method comprising;

patterning the gate electrode layer to form a second gate electrode in the second section of the at least one of the one or more active regions, wherein the second gate electrode has a second gate length smaller than the first gate length; and

forming second source and drain regions on opposing sides of the second gate electrode.

15. The method of claim 14 wherein the partially depleted transistor is a pull-down or a pull-up transistor of the SRAM cell.

16. The method of claim 14, further comprising:

after forming the first gate electrode, forming first source and drain extension regions in the first section and a first super halo region; and

after forming the second gate electrode, forming second source and drain extension regions in the second section and a second super halo region.

17. A method for forming an SRAM memory array, the method comprising:

providing a substrate, said substrate comprising a semiconductor layer overlying an insulator layer;

defining a plurality of active regions in the silicon layer;

forming a plurality of SRAM memory cells, each cell formed by;

forming a gate dielectric layer in at least one of the plurality of active regions;

forming a plurality of gate electrodes overlying the gate dielectric layer; and

forming first source and drain regions adjacent to respective ones of the plurality of gate electrodes to form a fully depleted FinFET transistor, the fully depleted FinFET transistor having a first channel length;

forming second source and drain regions adjacent to respective ones of the plurality of gate electrodes to form a partially depleted transistor, the partially depleted transistor having a second channel length that is less than the first channel length;

forming a plurality of complementary bit line pairs connected to respective ones of the plurality of SRAM memory cells; and

forming a plurality of word lines connected to respective ones of the plurality of SRAM memory cells.

18. The method of claim 17 wherein the fully depleted transistor is a pass-gate transistor of one of the plurality of SRAM memory cells.

19. The method of claim 17 wherein the partially depleted transistor is a pull-down or a pull-up transistor of one of the plurality of SRAM memory cells.

20. The method of claim 17 further comprising a step of forming a high-stress film covering the gate electrode, source region, and drain region of at least one of the fully depleted transistor or the partially depleted transistor.