Surround gate access transistors with grown ultra-thin bodies

• US 7,888,721 B2
• Filed: 07/06/2005
• Issued: 02/15/2011
• Est. Priority Date: 07/06/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard
• Primary Examiner(s): Pham; Thanh V
• Application Number:
  US11/175,677
• Publication Number:
  US 20070018206A1
• Time in Patent Office: 2,050 Days
• Field of Search: 257/302, 257/401, 257/191, 257/301, 257/329, 257/E29.262
• US Class Current: 257/301
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short channel effects with reduced need for high doping levels. Buried data/bit lines are formed in an upper surface of a substrate from which the transistors extend. The transistor can be formed asymmetrically or offset with respect to the data/bit lines. The offset provides laterally asymmetric source regions of the transistors. Continuous conductive paths are provided in the data/bit lines which extend adjacent the source regions to provide better conductive characteristics of the data/bit lines, particularly for aggressively scaled processes.

Claims

1. A transistor comprising:

a vertical annular semiconductive transistor body;

a surround gate structure formed around the annular transistor body;

a source region formed adjacent a lower portion of the body; and

a drain region formed adjacent an upper portion of the body such that the transistor defines a field effect transistor;

wherein the transistor body comprises a multiple grain region at an upper surface of the body and wherein the drain region is formed at the upper surface.

2. The transistor of claim 1, further comprising a pillar extending within the annular transistor body.

3. The transistor of claim 2, wherein the pillar comprises dielectric.

4. The transistor of claim 1, wherein the gate structure comprises a gate dielectric formed around and adjacent the annular transistor body and a gate conductor formed around and overlying the gate dielectric.

5. The transistor of claim 1, wherein the source region is formed asymmetrically biased on at least one side of the annular transistor body.

6. The transistor of claim 5, wherein conduction channels formed with appropriate potentials extend vertically and asymmetrically along the one side of the annular body.

7. A transistor comprising:

a vertical annular semiconductive transistor body;

a surround gate structure formed around the annular transistor body;

a source region formed adjacent a lower portion of the body; and

a drain region formed adjacent an upper portion of the body such that the transistor defines a field effect transistor;

wherein the source region is formed asymmetrically biased on at least one side of the annular transistor body.

8. The transistor of claim 7, further comprising a pillar extending within the annular transistor body.

9. The transistor of claim 8, wherein the pillar comprises dielectric.

10. The transistor of claim 7, wherein the gate structure comprises a gate dielectric formed around and adjacent the annular transistor body and a gate conductor formed around and overlying the gate dielectric.

11. The transistor of claim 7, wherein conduction channels formed with appropriate potentials extend vertically and asymmetrically along the one side of the annular body.