Three-dimensional integrated circuit structure

• US 7,888,764 B2
• Filed: 11/30/2006
• Issued: 02/15/2011
• Est. Priority Date: 06/24/2003
• Status: Expired due to Fees

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Lee, Sang-Yun
• Primary Examiner(s): Le; Thao P.
• Application Number:
  US11/606,523
• Publication Number:
  US 20070077694A1
• Time in Patent Office: 1,538 Days
• Field of Search: 257/44, 257/46, 257/104, 257/279, 257/367, 257/373, 257/461, 257/544, 257/653
• US Class Current: 257/461
• CPC Class Codes: H01L 21/76256 using silicon etch back techniques, e.g. BESOI, ELTRAN
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A semiconductor structure includes an interconnect region and a semiconductor stack bonded to the interconnect region through a bonding region. The stack includes at least two semiconductor layers having different electrical properties. The stack also includes single crystalline semiconductor material. The stack can be processed to form a mesa structure and the mesa structure can be processed to from a vertically oriented semiconductor device.

Claims

1. An apparatus, comprising:

a substrate which carries an electronic circuit and an interconnect region; and

a vertically oriented semiconductor device bonded to the interconnect region through a bonding region, the semiconductor device including a mesa structure having a pn junction.

2. The apparatus of claim 1, wherein the bonding region includes a metal layer.

3. The apparatus of claim 1, wherein opposed surfaces of the mesa structure include planarized surfaces.

4. The apparatus of claim 1, wherein the interconnect region includes a conductive line, the electronic circuit and vertically oriented semiconductor device being in communication with each other through the conductive line.

5. The apparatus of claim 1, wherein the vertically oriented semiconductor device is operated in response to a signal provided by the electronic circuit.

6. The apparatus of claim 1, wherein the mesa structure includes crystalline semiconductor material.

7. The apparatus of claim 1, wherein the vertically oriented semiconductor device includes a control terminal which adjusts the conductivity of the mesa structure in response to a signal from the electronic circuit.

8. An apparatus, comprising:

a substrate which carries an electronic circuit and interconnect region; and

a vertically oriented semiconductor device bonded to the interconnect region through a bonding region, the semiconductor device including a mesa structure having a pn junction and opposed planarized surfaces, wherein the pn junction extends between the opposed planarized surfaces.

9. The apparatus of claim 8, wherein the bonding region includes a metal material.

10. The apparatus of claim 9, wherein the vertically oriented semiconductor device is bonded to the interconnect region through a bonding interface established by the bonding region.

11. The apparatus of claim 10, wherein the bonding interface is not a growth interface.

12. The apparatus of claim 8, wherein the bonding region includes first and second conductive bonding layers with a bonding interface extending therebetween, wherein the electronic circuit is in communication with the vertically oriented semiconductor device through the interconnect region and first and second conductive bonding layers.