Apparatus and method for hardening latches in SOI CMOS devices

• US 7,888,959 B2
• Filed: 09/19/2007
• Issued: 02/15/2011
• Est. Priority Date: 09/19/2007
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Warnock, James D., Wendel, Dieter, Ning, Tak H., Cannon, Ethan H., Muller, K. Paul, Sigal, Leon J., KleinOsowski, AJ, Oldiges, Philip J.
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): ISLA RODAS, RICHARD
• Application Number:
  US11/857,596
• Publication Number:
  US 20090134925A1
• Time in Patent Office: 1,245 Days
• Field of Search: 327/112, 327/211, 327/199, 326/9, 326/13, 326/27, 324/762, 324/754, 324/765
• US Class Current: 324/762.01
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/356156 with synchronous operation

Abstract

A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

Claims

1. A method of determining one or more transistors within a particular latch to be respectively replaced with a hardened, series transistor, comprising:

identifying, as not requiring hardening, each transistor having only a gate terminal connected to a storage node of the latch;

identifying, as not requiring hardening, each transistor that remains ON upon both of the latch holding its state, and a respective storage node at logic state 0, and the latch holding its state, and the respective storage node at logic state 1;

identifying, as candidates for hardening, each transistor not previously identified as not requiring hardening; and

employing a hardened, series transistor in place of a transistor identified as a candidate for hardening.

2. The method of claim 1, wherein

the series transistor includes first and second series-connected transistors having a shared source/drain region and

a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

3. The method of claim 1, wherein

the candidates for hardening only include transistors being part of a cross-coupled inverter of the latch.

4. The method of claim 1, wherein a threshold voltage of the hardened, series transistor is lower than a threshold voltage of the transistor identified as a candidate for hardening.