IC tag, IC tag system, and method of executing command of the IC tag
First Claim
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1. An IC tag, comprising:
- a first storage circuit including a plurality of addressable memory cells;
a memory control circuit receiving a command and an address by use of a radio signal to control the first storage circuit based on the command and the address;
an address storage circuit storing the received address;
a second storage circuit containing relations of specific commands not requiring address data of memory cells to respective reference keys; and
a comparator circuit coupled to the address storage circuit and the second storage circuit, the comparator circuit comparing a received authorization key included in the received address with the reference keys,wherein when the received command is a command requiring address data, the memory control circuit performs a memory control in response to the received command and the address stored in the address storage circuit,wherein when the received command is a specific command not requiring address data, the comparator circuit compares the respective reference key related to the received specific command with the received authentication key included in the address received with the specific command stored in the address storage circuit and if the keys match the memory control circuit performs a memory control in response to the received command.
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Abstract
An IC tag according to an embodiment of the invention includes: a storage circuit having a plurality of memory cells; and a memory control circuit receiving commands by use of a radio signal to control the storage circuit based on the commands, the commands including a specific command to collectively control the plurality of memory cells, and the memory control circuit executing control corresponding to the specific command on the storage circuit based on the specific command and first key data received in association with the specific command.
14 Citations
14 Claims
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1. An IC tag, comprising:
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a first storage circuit including a plurality of addressable memory cells; a memory control circuit receiving a command and an address by use of a radio signal to control the first storage circuit based on the command and the address; an address storage circuit storing the received address; a second storage circuit containing relations of specific commands not requiring address data of memory cells to respective reference keys; and a comparator circuit coupled to the address storage circuit and the second storage circuit, the comparator circuit comparing a received authorization key included in the received address with the reference keys, wherein when the received command is a command requiring address data, the memory control circuit performs a memory control in response to the received command and the address stored in the address storage circuit, wherein when the received command is a specific command not requiring address data, the comparator circuit compares the respective reference key related to the received specific command with the received authentication key included in the address received with the specific command stored in the address storage circuit and if the keys match the memory control circuit performs a memory control in response to the received command. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 11, 12)
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10. An IC tag system, comprising:
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a reader/writer transmitting command data and address data by use of a radio signal; and an IC tag receiving the radio signal sent from the reader/writer, the IC tag comprising; a first storage circuit including a plurality of addressable memory cells storing data; a memory control circuit receiving a command and an address based on the command data and address data to control the first storage circuit, an address storage circuit storing the received address; a second storage circuit containing relations of specific commands not requiring address data of memory cells to respective reference keys; and a comparator circuit coupled to the address storage circuit and the second storage circuit, the comparator circuit comparing a received authorization key included in the received address with the reference keys, wherein when the reader/writer transmits a specific command not requiring address data, the reader/writer transmits the authentication key as the address data, wherein when the received command is a command requiring address, the memory control circuit performs a memory control in response to the received command and the address stored in the address storage circuit, wherein when the received command is a specific command not requiring address data, the comparator circuit compares the reference key related to the received specific command with the received authentication key included in the address received with the specific command stored in the address storage circuit and if the keys match the memory control circuit performs a memory control in response to the received command. - View Dependent Claims (13, 14)
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Specification
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Current AssigneeRenesas Electronics Corporation
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Original AssigneeRenesas Electronics Corporation
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InventorsAkiyama, Kazuhiro, Uchino, Tatsuya, Seki, Kazumi, Okamoto, Seiichi, Igarashi, Hatsuhide, Miyashita, Toshiyuki
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Primary Examiner(s)Lee; Benjamin C
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Assistant Examiner(s)Eustaquio; Cal
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Application NumberUS11/526,627Publication NumberTime in Patent Office1,603 DaysField of Search340/51, 340/824.54, 340/10.1, 340/10.5, 340/825.52US Class Current340/10.1CPC Class CodesG06K 19/0723 the record carrier comprisi...
