Current mirror circuit and digital-to-analog conversion circuit

• US 7,889,106 B2
• Filed: 08/11/2010
• Issued: 02/15/2011
• Est. Priority Date: 02/13/2008
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Imai, Shigeo
• Primary Examiner(s): JEANGLAUDE, JEAN BRUNER
• Application Number:
  US12/854,480
• Publication Number:
  US 20100321223A1
• Time in Patent Office: 188 Days
• Field of Search: 341/150, 341/144, 341/136, 341/141, 341/154
• US Class Current: 341/136
• CPC Class Codes: G05F 3/262 using field-effect transistors only
• CPC Class Codes: H03M 1/742 using current sources as quantisation value generators

Abstract

A first switched capacitor circuit is connected to the source of one MOS transistor of a current mirror pair configured by a pair of MOS transistors and a second switched capacitor circuit is connected to the source of the other MOS transistor. Each of the first and second switched capacitor circuits includes a capacitor and a switch connected in parallel with the capacitor and the switch is on/off-controlled based on a clock signal of a preset cycle. Each of the first and second switched capacitor circuits equivalently functions as a resistor with large resistance and a variation in the output current of the current mirror circuit based on a variation in the threshold voltages of the pair of MOS transistors can be reduced even if the power source voltage is reduced.

Claims

1. A digital-to-analog conversion circuit comprising:

a first MOS transistor having a gate, drain and source;

an operational amplifier that has an inverted input node, non-inverted input node and output node and in which the inverted input node is supplied with a reference voltage and the non-inverted input node and output node are respectively connected to the drain and gate of the first MOS transistor;

a first resistor connected between a first power source voltage node and the drain of the first MOS transistor;

a plurality of second MOS transistors having gates, drains and sources, the gates being connected to the gate of the first MOS transistor and the second MOS transistors configuring a plurality of current mirror pairs together with the first MOS transistor;

a first switched capacitor circuit connected between the source of the first MOS transistor and a second power source voltage node;

a plurality of second switched capacitor circuits connected between the sources of the plurality of second MOS transistors and the second power source voltage node;

a second resistor having one end and the other end, the one end being connected to the first power source voltage node and the other end being connected to a first analog voltage output node;

a third resistor having one end and the other end, the one end being connected to the first power source voltage node and the other end being connected to a second analog voltage output node; and

a plurality of switching circuits that are respectively connected between the first and second analog voltage output nodes and the drains of the plurality of second MOS transistors and permit currents flowing through the plurality of second MOS transistors to flow through one of the first and second analog voltage output nodes that are selectively switched based on plural-bit digital signals.

2. The digital-to-analog conversion circuit according to claim 1, wherein the first MOS transistor and the plurality of second MOS transistors are N-channel MOS transistors.

3. The digital-to-analog conversion circuit according to claim 1, wherein the first switched capacitor circuit includes a first capacitor and a first switch connected in parallel with the first capacitor, and each of the plurality of second switched capacitor circuits includes a second capacitor and a second switch connected in parallel with the second capacitor.

4. The digital-to-analog conversion circuit according to claim 3, wherein the first switch is a switch that is on/off-controlled on a preset cycle, and the second switch is a switch that is on/off-controlled on the same cycle as the first switch and in the same phase as the first switch.

5. The digital-to-analog conversion circuit according to claim 3, wherein capacitances of the first and second capacitors are set to the same value.