Analog digital converter, A/D conversion stage, method for generating digital signal corresponding to analog signal, and method for generating signal indicating conversion error in the A/D conversion stage

• US 7,889,111 B2
• Filed: 06/08/2007
• Issued: 02/15/2011
• Est. Priority Date: 06/08/2006
• Status: Expired due to Fees

• Current Assignee: National University Corporation Shizuoka University
• Original Assignee: National University Corporation Shizuoka University
• Inventors: Kawahito, Shoji
• Primary Examiner(s): WILLIAMS, HOWARD L
• Application Number:
  US12/303,909
• Publication Number:
  US 20090243900A1
• Time in Patent Office: 1,348 Days
• Field of Search: 341/118, 341/120, 341/161, 341/162, 341/163, 341/172
• US Class Current: 341/162
• CPC Class Codes: H03M 1/0695 using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
• CPC Class Codes: H03M 1/144 the steps being performed sequentially in a single stage, i.e. recirculation type H03M1/141, H03M1/143, H03M1/16 take precedence
• CPC Class Codes: H03M 1/146 all stages being simultaneous converters

Abstract

A conversion operation B is performed with respect to a sample value R in an A/D conversion stage 101 to generate a conversion result D3, and a sampling operation A is performed with respect to this conversion result D3 in an A/D conversion stage 103. The conversion operation B is performed with respect to a sample value in an A/D conversion stage 105 to generate a conversion result D4, and the sampling operation A is performed with respect to the conversion result D4 in an A/D conversion stage 107. The conversion operation B is performed with respect to a sample value in an A/D conversion stage 107 to generate a conversion result D5, and the sampling operation A is performed with respect to this conversion result D5 in an A/D conversion stage 101. The conversion operation B is performed with respect to a sample value in the A/D conversion stage 103 to generate a conversion result D6, and the sampling operation A is performed with respect to the conversion result D6 in the A/D conversion stage 105.

Claims

1. An analog-digital converter comprising:

first to N-th A/D conversion stages connected in series, each stage having a stage input and a stage output, each of the first to N-th A/D conversion stages including a sub A/D conversion circuit, a control circuit, a D/A converter and a gain stage, the sub A/D conversion circuit generating a digital signal of a predetermined number of bits in response to a signal from the stage input, the digital signal indicating a conversion result, the control circuit generating a control signal from the digital signal, the D/A converter generating a predetermined voltage in accordance with the control signal, the gain stage having a first input, a second input and an output, the first input of the gain stage receiving the signal from the stage input, the second input of the gain stage receiving one of the predetermined voltage and the signal from the stage input, the output of the gain stage being connected to the stage output, and the number “

N”

being 3 or 4;

an analog input for receiving an analog signal;

an input switch, connected between the analog input and the stage input of the first A/D conversion stage, for sampling first and second sample analog signals in first and second sampling periods, respectively;

a cyclic switch, connected between the stage input of the first A/D conversion stage and the stage output of the N-th A/D conversion stage, for providing a path from the N-th A/D conversion stage to the first A/D conversion stage in a cycle period, the cycle period being different from the first and second sampling periods; and

a digital operational circuit, the digital operational circuit receiving the conversion result from each of the first to N-th A/D conversion stages, the digital operational circuit generating an A/D conversion digital code, and the A/D conversion digital code indicating a analog/digital conversion result;

wherein the gain stage has first and second capacitors and an operational amplification circuit,

the gain stage stores electric charges from the stage input in the first and second capacitors, again stores an electric charge from the stage input in one of the first and second capacitors, rearranges the electric charges using the first and second capacitors and the operational amplification circuit in response to application of the predetermined voltage to one of the first and second capacitors, and rearranges the rearranged electric charges in the first and second capacitors in response to application of the predetermined voltage to another one of the first and second capacitors to generate the operational value in the output of the operational amplification circuit; and

the gain stage comprises;

a first switch for connecting one terminal of the first capacitor to the stage input in a first period;

a second switch for connecting one terminal of the second capacitor to the stage input in the first period;

a third switch for connecting the one terminal of the first capacitor to the output of the operational amplification circuit in a second period, the second period being different from the first period;

a fourth switch, connected between the other terminal of the first capacitor and an inverting input of the operational amplification circuit, for disconnecting the other terminal of the first capacitor from the inverting input in a third period, the third period being between the first period and the second period; and

a fifth switch, connected between the one terminal of the second capacitor and the output of the operational amplification circuit, for connecting the one terminal of the second capacitor to the output of the operational amplification circuit in a fourth period that is different from the first to third periods, and

wherein the inverting input of the operational amplification circuit is connected to another terminal of the first capacitor and to another terminal of the second capacitor in the second period, and the output of the operational amplification circuit is connected to the stage output, and

wherein the D/A converter provides the predetermined voltage to the one terminal of the second capacitor in the second period and provides the predetermined voltage to the one terminal of the first capacitor in the fourth period.

2. The analog-digital converter according to claim 1,

wherein the number N of the series-connected first to N-th A/D conversion stages is 4;

the gain stage has first and second capacitors and an operational amplification circuit; and

the gain stage stores electric charges from the stage input in the first and second capacitors, rearranges the electric charges stored in the first and second capacitors in response to application of the predetermined voltage to one of the first and second capacitors to generate an operational value in an output of the operational amplification circuit.

3. The analog-digital converter according to claim 2,

wherein the gain stage includes:

a first switch for connecting one terminal of the first capacitor to the stage input in a first period;

a second switch for connecting one terminal of the second capacitor to the stage input in the first period; and

a third switch for connecting the one terminal of the first capacitor to the output of the operational amplification circuit in a second period, the second period being different from the first period,

wherein an inverting input of the operational amplification circuit is connected to another terminal of the first capacitor and to another terminal of the second capacitor in the second period, and the output of the operational amplification circuit is connected to the stage output, and

wherein the D/A converter provides the predetermined voltage to the one terminal of the second capacitor in the second period.

4. The analog-digital converter according to any one of claims 2, 3 and 1, wherein the digital operational circuit includes:

first to fourth storage circuits for storing digital signals from the first to fourth A/D conversion stages, respectively, the digital signals being divided into first and second data groups, the first data group being composed of the digital signals associated with the first sample analog signal, and the second data group being composed of the digital signals associated with the second sample analog signal;

a first circuit, connected to the first to fourth storage circuits, for generating a first digital code by using the digital signals of the first data group, the first digital code being associated with the first sample analog signal;

a second circuit, connected to the first to fourth storage circuits, for generating a second digital code by using the digital signals of the second data group, the second digital code being associated with the second sample analog signal; and

a correction circuit for correcting one of the first and second digital codes using another of the first and second digital codes to generate the A/D conversion digital code.

5. The analog-digital converter according to claim 2, wherein the gain stage in each A/D conversion stage generates a mismatch value in the output of the operational amplification circuit, the mismatch value indicates an error due to mismatch in capacitance of the first capacitor and the second capacitor;

and each of the first to fourth A/D conversion stages provides an operation signal for the mismatch value in the cycle period.

6. The analog-digital converter according to claim 5, wherein

the gain stage has first and second mismatch correction operations;

in the first mismatch correction operation, an input and the output of the operational amplification circuit and the second capacitor are connected to each other to equalize electric potentials of the operational amplification circuit and the second capacitor, an electric charge is stored in the first capacitor in response to application of a reference signal to the first capacitor, and the D/A converter provides the reference signal; and

in the second mismatch correction operation, the electric charge is rearranged in the first and second capacitors in response to application of the reference signal to the second capacitor to generate the mismatch value in the output of the operational amplification circuit.

7. The analog-digital converter according to claim 5,

wherein the first and second capacitors are connected to the stage input in a first period to sample the analog signal;

wherein the D/A converter provides the predetermined voltage to one terminal of the second capacitor in a second period for processing the analog signal, provides one terminal of the second capacitor with a reference potential in a third period for receiving a signal for compensating the mismatch in capacitance, provides a reference voltage to the one terminal of the first capacitor in the third period, and provides the reference voltage to the one terminal of the second capacitor in the fourth period for processing the signal for compensating the mismatch in capacitance; and

wherein the gain stage includes;

a feedback switch for connecting an inverting input of the operational amplification circuit to the output of the operational amplification circuit in the first and third periods; and

a first switch for connecting the one terminal of the first capacitor to the output of the operational amplification circuit in the second and fourth periods.

8. The analog-digital converter according to claim 2,

wherein the gain stage in each A/D conversion stage generates a gain error value in the output of the operational amplification circuit, and the gain error value indicates an finite gain error due to a finite gain of the operational amplification circuit;

and

wherein each of the first to fourth A/D conversion stages generates an operational value for the gain error value in the cycle period.

9. The analog-digital converter according to claim 8,

wherein the gain stage has first and second finite gain correction operations;

in the first finite gain correction operation, the input and the output of the operational amplification circuit are connected to each other to equalize an electric potential of the operational amplification circuit, and electric charges are stored in the first and second capacitors in response to application of a reference signal to the first and second capacitors, and the D/A converter provides the reference signal;

in the second finite gain correction operation, the first capacitor is connected to the input and the output of the operational amplification circuit to rearrange the electric charges in the first and second capacitors in response to application of the reference signal to the second capacitor, and the gain error value is generated in the output of the operational amplification circuit.

10. The analog-digital converter according to claim 8,

wherein the first and second capacitors are connected to the stage input in a first period for sampling the analog signal;

the D/A converter provides the predetermined voltage to one terminal of the second capacitor in a second period for processing the analog signal, provides a reference voltage to the one terminal of the second capacitor in a third period for receiving a signal for compensating the finite gain error and a fourth period for processing the signal for compensating the finite gain error, and provides the reference signal to one terminal of the first capacitor in the third period; and

wherein the gain stage includes;

a feedback switch for connecting an inverting input of the operational amplification circuit to the output of the operational amplification circuit in the first and third periods; and

a first switch for connecting the one terminal of the first capacitor to the output of the operational amplification circuit in the second and fourth periods.

11. The analog-digital converter according to claim 2,

wherein, in each of the first to fourth A/D conversion stages, the first and second capacitors are connected to the stage input in a first period for sampling the analog signal;

the D/A converter provides the predetermined voltage to one terminal of the second capacitor in a second period for processing the analog signal, provides the one terminal of the second capacitor with a reference potential in a third period for receiving a signal for compensating the mismatch in capacitance, provides a reference voltage to the one terminal of the second capacitor in a fourth period for processing the signal for compensating the mismatch in capacitance, a fifth period for receiving a signal for compensating the finite gain error, and a sixth period for processing the signal for compensating the finite gain error, and provides the reference voltage to one terminal of the first capacitor in the fifth period and the third period; and

the gain stage includes;

a feedback switch for connecting an inverting input of the operational amplification circuit to the output of the operational amplification circuit in the first, third, and fifth periods; and

a first switch for connecting the one terminal of the first capacitor to the output of the operational amplification circuit in the second, fourth, and sixth periods.

12. The analog-digital converter according to any one of claims 5 to 11, wherein

the digital operational circuit generates a correction digital code, and corrects a digital code by using the correction digital code, the digital code is associated with the analog signal and is generated from the digital signals from the first to fourth A/D conversion stages, and the correction digital code represents an error due to at least one from among an offset of a sample/hold circuit, a noise caused by a feedback switching of the sample/hold circuit, the mismatch in capacitance in the first to fourth A/D conversion stages, and the finite gain error of each gain stage of the first to fourth A/D conversion stages.

13. The analog-digital converter according to claim 1,

wherein the number “

N”

of the series-connected first to N-th A/D conversion stages is 3;

the gain stage has a first to third capacitors and an operational amplification circuit; and

the gain stage stores electric charges from the stage input in the first and second capacitors, the electric charges are rearranged in the first and second capacitors in response to application of the predetermined voltage to the first capacitor to generate an operational result in the output of the operational amplification circuit, the gain stage stores an electric charge in the third capacitor, this electric charge being associated with the operational result, the rearranged electric charges are rearranged in the first to third capacitor in response to application of the predetermined voltage to the second capacitor to generate the operational value in the output of the operational amplification circuit.

14. The analog-digital converter according to claim 13,

wherein the gain stage includes:

a first switch for connecting one terminal of the first capacitor to the stage input in a first period;

a second switch for connecting one terminal of the second capacitor to the stage input in the first period;

a third switch, connected between the one terminal of the second capacitor and the output of the operational amplification circuit, for connecting the one terminal of the second capacitor to the output of the operational amplification circuit in a second period, the second period being different from the first period;

a fourth switch, connected between the one terminal of the first capacitor and the output of the operational amplification circuit, for connecting the one terminal of the first capacitor to the output in a third period, the third period being different from the first and second periods;

a fifth switch, connected between one terminal of the third capacitor and the inverting input of the operational amplification circuit, for connecting the one terminal of the third capacitor to the inverting input of the operational amplification circuit in the third period; and

a sixth switch, connected between the one terminal of the third capacitor and a reference potential line, for providing the reference potential to the one terminal of the third capacitor in the first and second periods;

wherein the inverting input of the operational amplification circuit is connected to another terminal of the first capacitor and to another terminal of the second capacitor, and the output of the operational amplification circuit is connected to another terminal of the third capacitor and to the stage output; and

wherein the D/A converter provides the predetermined voltage to the one terminal of the first capacitor in the second period, and provides the predetermined voltage to the one terminal of the second capacitor in the third period.

15. The analog-digital converter according to claim 13 or 14,

wherein the digital operational circuit includes:

first to third storage circuits for storing digital signals from the first to third A/D conversion stages, respectively, the digital signals being divided into first and second data groups, the first data group being composed of the digital signals associated with the first sample analog signal, and the second data group being composed of the digital signals associated with the second sample analog signal;

a first circuit, connected to the first to third storage circuits, for generating a first digital code by using the digital signals of the first data group, the first digital code being associated with the first sample analog signal;

a second circuit, connected to the first to third storage circuits, for generating a second digital code by using the digital signals of the second data group, the second digital code being associated with the second sample analog signal; and

a correction circuit for correcting one of the first and second digital codes using another of the first and second digital codes to generate the A/D conversion digital code.

16. The analog-digital converter according to claim 1, wherein the sub A/D conversion circuit comprises a comparator, the comparator compares a signal from the stage input with a predetermined reference signal, and the sub A/D conversion circuit provides a comparison result signal.

17. The analog-digital converter according to claim 1, wherein the sub A/D conversion circuit compares a signal from the stage input with two predetermined reference signals to generate a three-value redundant digital signal.

18. The analog-digital converter according to claim 1, further comprising

a sample/hold circuit having an input that receives an input analog signal, and an output that provides the analog signal to the analog input, the sample/hold circuit comprising an operational amplification circuit, the operational amplification circuit having an inverting input, a non-inverting output and a feedback switch, and the feedback switch being connected between the inverting input and the non-inverting output.

19. The analog-digital converter according to claim 18, wherein the operational amplification circuit of the sample/hold circuit further comprises a non-inverting input and an inverting output;

and the sample/hold circuit comprises another feedback switch connected between the non-inverting input of the operational amplification circuit and the inverting output of the operational amplification circuit.

20. An analog-digital converter comprising:

first to N-th A/D conversion stages connected in series, each stage having a stage input and a stage output, each of the first to N-th A/D conversion stages including a sub A/D conversion circuit, a control circuit, a D/A converter and a gain stage, the sub A/D conversion circuit generating a digital signal of a predetermined number of bits in response to a signal from the stage input, the digital signal indicating a conversion result, the control circuit generating a control signal from the digital signal, the D/A converter generating a predetermined voltage in accordance with the control signal, the gain stage having a first input, a second input and an output, the first input of the gain stage receiving the signal from the stage input, the second input of the gain stage receiving one of the predetermined voltage and the signal from the stage input, the output of the gain stage being connected to the stage output, and the number “

N”

being 3 or 4;

an analog input for receiving an analog signal;

an input switch, connected between the analog input and the stage input of the first A/D conversion stage, for sampling first and second sample analog signals in first and second sampling periods, respectively;

a cyclic switch, connected between the stage input of the first A/D conversion stage and the stage output of the N-th A/D conversion stage, for providing a path from the N-th A/D conversion stage to the first A/D conversion stage in a cycle period, the cycle period being different from the first and second sampling periods;

a digital operational circuit, the digital operational circuit receiving the conversion result from each of the first to N-th A/D conversion stages, the digital operational circuit generating an A/D conversion digital code, and the A/D conversion digital code indicating a analog/digital conversion result; and

a sample/hold circuit having an input that receives an input analog signal, and an output that provides the analog signal to the analog input, the sample/hold circuit comprising an operational amplification circuit, the operational amplification circuit having an inverting input, a non-inverting output and a feedback switch, and the feedback switch being connected between the inverting input and the non-inverting output;

wherein one of the first and second sample analog signals is prepared as the input analog signal, and the feedback switch of the sample/hold circuit is opened in the entire period of one of the first and second sampling periods.

21. The analog-digital converter according to claim 20, wherein the feedback switch of the sample/hold circuit is closed in another of the first and second sampling periods;

and another of the first and second sample analog signals is provided after the feedback switch of the sample/hold circuit is opened.

22. An A/D conversion stage comprising:

a stage input;

a stage output;

a sub A/D conversion circuit that generates a digital signal in response to an analog signal from the stage input, the digital signal indicating a conversion result of a predetermined number of bits;

a control circuit that generates a control signal, the control signal being associated with the digital signal; and

a gain stage having a first input, a second input and an output, the first input receiving an analog signal from the stage input, the second input receiving the control signal, and the output being connected to the stage output,

the gain stage including;

a first capacitor having one terminal and another terminal;

a second capacitor having one terminal and another terminal;

a first sampling switch for connecting the one terminal of the first capacitor to the stage input in a first period for sampling the analog signal;

a second sampling switch for connecting the one terminal of the second capacitor to the stage input in the first period;

an operational amplification circuit having an inverting input and an output, the inverting input being connected to the other terminal of the first capacitor and to the other terminal of the second capacitor, and the output being connected to the stage output;

a D/A converter having first and second outputs, the first and second outputs being connected to the one terminal of the first capacitor and the one terminal of the second capacitor, respectively, the D/A converter providing a predetermined voltage to the one terminal of the second capacitor in a second period for processing the analog signal, the predetermined voltage being associated with the control signal, the D/A converter providing the one terminal of the second capacitor with a reference potential in a third period for receiving a signal for compensating mismatch in capacitance, the D/A converter providing a reference voltage to the one terminal of the second capacitor in a fourth period for processing the signal for compensating the mismatch in capacitance, a fifth period for receiving a signal for correcting a finite gain, and a sixth period for processing the signal for correcting a finite gain, and the D/A converter providing the reference voltage to the one terminal of the first capacitor in the fifth period and the third period;

a feedback switch for connecting the inverting input to the output of the operational amplification circuit in the first, third, and fifth periods; and

a first switch for connecting the one terminal of the first capacitor to the output of the operational amplification circuit in the second, fourth, and sixth periods.

23. An A/D conversion stage comprising:

a stage input;

a stage output;

a sub A/D conversion circuit that generates a digital signal in response to application of an analog signal from the stage input, the digital signal indicating a conversion result of a predetermined number of bits;

a control circuit that generates a control signal, the control signal being associated with the digital signal; and

a gain stage having a first input, a second input and an output, the first input receiving an analog signal from the stage input, the second input receiving the control signal, and the output being connected to the stage output,

the gain stage including;

a first capacitor having one terminal and another terminal;

a second capacitor having one terminal and another terminal;

a first sampling switch for connecting the one terminal of the first capacitor to the stage input in a first period for sampling the analog signal;

a second sampling switch for connecting the one terminal of the second capacitor to the stage input in the first period;

an operational amplification circuit having an inverting input and an output, the inverting input being connected to the other terminal of the first capacitor and to the other terminal of the second capacitor, and the output being connected to the stage output;

a D/A converter having first and second outputs, the first and second outputs being connected to the one terminal of the first capacitor and the one terminal of the second capacitor, respectively, the D/A converter providing a predetermined voltage to the one terminal of the second capacitor in a second period for processing the analog signal, the predetermined voltage being associated with the control signal, the D/A converter providing the one terminal of the second capacitor with a reference potential in a third period for receiving a signal for compensating mismatch in capacitance, the D/A converter providing a reference voltage to the one terminal of the first capacitor in the third period, and the D/A converter providing the reference voltage to the one terminal of the second capacitor in a fourth period for processing the signal for compensating the mismatch in capacitance;

a feedback switch for connecting the inverting input to the output of the operational amplification circuit in the first and third periods; and

a first switch for connecting the one terminal of the first capacitor to the output of the operational amplification circuit in the second and fourth periods.

24. An A/D conversion stage comprising:

a stage input;

a stage output;

a sub A/D conversion circuit that generates a digital signal in response to a signal from the stage input, the digital signal indicating a conversion result of a predetermined number of bits;

a control circuit that generates a control signal, the control signal being associated with the digital signal; and

a gain stage having a first input, a second input and an output, the first input receiving an analog signal from the stage input, the second input receiving the control signal, and the output being connected to the stage output,

the gain stage including;

a first capacitor having one terminal and another terminal;

a second capacitor having one terminal and another terminal;

a first sampling switch for connecting the one terminal of the first capacitor to the stage input in a first period for sampling the analog signal;

a second sampling switch for connecting the one terminal of the second capacitor to the stage input in the first period;

an operational amplification circuit having an inverting input and an output, the inverting input being connected to the other terminal of the first capacitor and to the other terminal of the second capacitor, and the output being connected to the stage output;

a D/A converter having first and second outputs, the first and second outputs being connected to the one terminal of the first capacitor and the one terminal of the second capacitor, respectively, the D/A converter providing a predetermined voltage to the one terminal of the second capacitor in a second period for processing the analog signal, the predetermined voltage being associated with the control signal, the D/A converter providing a reference signal to the one terminal of the second capacitor in a third period for receiving a signal for compensating a finite gain error and a fourth period for processing the signal for compensating the finite gain error, and the D/A converter providing the reference signal to the one terminal of the first capacitor in the third period;

a feedback switch for connecting the inverting input to the output of the operational amplification circuit in the first and third periods; and

a first switch for connecting the one terminal of the first capacitor to the output of the operational amplification circuit in the second and fourth periods.

25. A method of generating a digital signal corresponding to an analog signal by using a gain stage, the gain stage comprising first and second capacitors and an operational amplification circuit, the method comprising the steps of:

(a) generating a digital signal having a digital value of a predetermined number of bits, the digital signal being associated with one of first and second input analog signals;

(b) storing an electric charge in the first capacitor and an electric charge in the second capacitor, the electric charges being associated with the first input analog signal;

(c) after the electric charges has been stored in the first and second capacitors, holding the electric charge in one of the first capacitor and the second capacitor, and sampling the second input analog signal to store an electric charge in another of the first capacitor and the second capacitor, and the electric charge being associated with the second input analog signal;

(d) after the sampling has been performed for the first and second capacitors, connecting the first capacitor between an output of the operational amplification circuit and an inverting input of the operational amplification circuit, and supplying a conversion analog signal to one terminal of the second capacitor to generate a first conversion value for the output of the operational amplification circuit and to rearrange the electric charges stored in the first and second capacitors, the conversion analog signal being associated with the digital signal; and

(e) after the sampling has been performed in the first and second capacitors, connecting the second capacitor between the output and the inverting input of the operational amplification circuit, and supplying the conversion analog signal to one terminal of the first capacitor to generate a second conversion value for the output of the operational amplification circuit and to rearrange the electric charges stored in the first and second capacitors.

26. The method according to claim 25, further comprising the steps of:

sampling a signal to a sample/hold circuit, bringing the sample/hold circuit to a holding operation state to hold the sampled signal, and providing the held signal as one of the first and second sample analog signals, the sample/hold circuit having an operational amplification circuit; and

closing a switch connected between an input of the operational amplification circuit of the sample/hold circuit and an output of the operational amplification circuit of the sample/hold circuit, opening the closed switch to bring the sample/hold circuit to a holding operation state, and preparing the held signal as another one of the first and second sample analog signals.

27. A method of generating a digital signal corresponding to an analog signal by using first to fourth A/D conversion stages, each of the first to fourth A/D conversion stages comprising first and second capacitors and an operational amplification circuit, the method comprising the steps of:

(a) performing a predetermined conversion operation of an analog signal sampled in the first A/D conversion stage to generate a first conversion result in the first A/D conversion stage, performing a predetermined sampling operation of an first analog signal in the second A/D conversion stage, performing the predetermined conversion operation of an analog signal sampled in the third A/D conversion stage to generate a second conversion result in the third A/D conversion stage, and performing the predetermined sampling operation of an second analog signal in the fourth A/D conversion stage, the first analog signal being associated with the first conversion result, and the second analog signal being associated with the second conversion result;

(b) performing the predetermined conversion operation of an analog signal sampled in the fourth A/D conversion stage to generate a third conversion result in the fourth A/D conversion stage, performing the predetermined sampling operation of an third analog signal in the first A/D conversion stage, performing the predetermined conversion operation of an analog signal sampled in the second A/D conversion stage to generate a fourth conversion result in the second A/D conversion stage, and performing the predetermined sampling operation of an fourth analog signal in the third A/D conversion stage, the third analog signal being associated with the third conversion result, and the fourth analog signal being associated with the fourth conversion result; and

(c) repeating the step (a) and the step (b),

wherein the predetermined sampling operation comprises the step of storing electric charges in the first capacitor and the second capacitor, the electric charges being associated with an input analog signal supplied to the relevant A/D conversion stage; and

wherein the predetermined conversion operation comprises the step of connecting the first capacitor between an output of the operational amplification circuit and an inverting input of the operational amplification circuit, and supplying a conversion analog signal to one terminal of the second capacitor to generate a conversion value in the output of the operational amplification circuit and rearrange the electric charges stored in the first and second capacitors, the conversion analog signal being associated with a digital signal, and the digital signal indicating an A/D conversion result in the relevant A/D conversion stage.

28. The method according to claim 27, comprising the steps of:

prior to the steps (a) and (b), receiving a first sample analog signal in the first A/D conversion stage, and performing the predetermined sampling operation of the first sample analog signal;

performing the predetermined conversion operation of an analog signal sampled in the first A/D conversion stage to generate a fifth conversion result in the first A/D conversion stage, and performing the predetermined sampling operation of an fifth analog signal in the second A/D conversion stage, the fifth analog signal being associated with the fifth conversion result;

receiving a second sample analog signal in the first A/D conversion stage, performing the predetermined sampling operation of the second sample analog signal, performing the predetermined conversion operation of an analog signal sampled in the second A/D conversion stage to generate a sixth conversion result in the second A/D conversion stage, and performing the predetermined sampling operation of a six analog signal in the third A/D conversion stage, the six analog signal being associated with the sixth conversion result.

29. A method of generating a digital signal corresponding to an analog signal by using first to fourth A/D conversion stages, each of the first to fourth A/D conversion stages having first and second capacitors and an operational amplification circuit, the method comprising the steps of:

(a) performing a first conversion operation of an analog signal sampled in the first A/D conversion stage to generate a first conversion result in the first A/D conversion stage, performing a first sampling operation of a first analog signal in the second A/D conversion stage, performing the first conversion operation of an analog signal sampled in the third A/D conversion stage to generate a second conversion result in the third A/D conversion stage, and performing the first sampling operation of a second analog signal in the fourth A/D conversion stage, the first analog signal being associated with the first conversion result, and the second analog signal being associated with the second conversion result;

(b) performing a second conversion operation in the first A/D conversion stage to generate a third conversion result in the first A/D conversion stage after the first conversion operation in the first A/D conversion stage, performing a second sampling operation of a third analog signal in the second A/D conversion stage, performing the second conversion operation in the third A/D conversion stage to generate a fourth conversion result in the third A/D conversion stage after the first conversion operation in the third A/D conversion stage, and performing the second sampling operation of a fourth analog signal in the fourth A/D conversion stage, the third analog signal being associated with the third conversion result, and the fourth analog signal being associated with the fourth conversion result;

(c) performing the first conversion operation of an analog signal sampled in the second A/D conversion stage to generate a fifth conversion result, performing the first sampling operation of an fifth analog signal in the third A/D conversion stage, performing the first conversion operation in the fourth A/D conversion stage to generate a sixth conversion result in the fourth A/D conversion stage, and performing the first sampling operation of a sixth analog signal in the first A/D conversion stage, the fifth analog signal being associated with the fifth conversion result, and the sixth analog signal being associated with the sixth conversion result;

(d) performing the second conversion operation to generate a seventh conversion result after the first conversion operation in the second A/D conversion stage, performing the second sampling operation of a seventh analog signal in the third A/D conversion stage, performing the second conversion operation in the fourth A/D conversion stage to generate an eighth conversion result in the fourth A/D conversion stage after the first conversion operation in the fourth A/D conversion stage, and performing the second sampling operation in the first A/D conversion stage of a eighth analog signal, the seventh analog signal being associated with the seventh conversion result, and the eighth analog signal being associated with the eighth conversion result,

wherein the first sampling operation comprises the step of storing an electric charge in the first capacitor and storing an electric charge in the second capacitor, the electric charge corresponding to a first input analog signal;

wherein the second sampling operation comprises the step of, prior to rearranging the electric charges of the first and second capacitors, holding an electric charge of one of the first capacitor and the second capacitor, and sampling an electric charge in another of the first capacitor and the second capacitor, this electric charge corresponding to a second analog signal;

wherein the first conversion operation comprises the step of connecting the first capacitor between the output of the operational amplification circuit and an inverting input of the operational amplification circuit, and supplying a conversion analog signal to another terminal of the second capacitor to generate a first conversion value for a subsequent A/D conversion stage in the output of the operational amplification circuit and to rearrange the electric charges of the first and second capacitors, the first conversion value being associated with a first input analog signal, the conversion analog signal being associated with a digital signal, and the digital signal indicating an A/D conversion result in the relevant A/D conversion stage; and

wherein the second conversion operation comprises the step of connecting the second capacitor between the output of the operational amplification circuit and the inverting input of the operational amplification circuit, and supplying a conversion analog signal to the other terminal of the first capacitor to generate a second conversion value for a subsequent A/D conversion stage in the output of the operational amplification circuit and to rearrange the electric charges of the first and second capacitors, the second conversion value being associated with a second input analog signal, the conversion analog signal being associated with a digital signal, and the digital signal indicating an A/D conversion result in the relevant A/D conversion stage.

30. The method according to claim 29, further comprising a step of successively repeating the step (a) to the step (d).

31. The method according to claim 29, comprising the steps of:

prior to the steps (a) to (d), receiving a first sample analog signal in the first A/D conversion stage and successively performing the first and second sampling operations of the first sample analog signal;

performing a first conversion operation of an analog signal sampled in the first A/D conversion stage to generate a ninth conversion result in the first A/D conversion stage, and performing a first sampling operation of a ninth analog signal in the second A/D conversion stage, the ninth analog signal corresponding to the ninth conversion result;

after the first conversion operation in the first A/D conversion stage, performing a second conversion operation in the first A/D conversion stage to generate a tenth conversion result in the first A/D conversion stage, and performing a second sampling operation of a tenth analog signal in the second A/D conversion stage, the tenth analog signal being associated with the tenth conversion result;

receiving a second sample analog signal in the first A/D conversion stage, performing the first sampling operation of the second sample analog signal, performing the first conversion operation of an analog signal sampled in the second A/D conversion stage to generate an eleventh conversion result in the second A/D conversion stage, and performing the first sampling operation of an eleventh analog signal in the third A/D conversion stage, the eleventh analog signal being associated with the eleventh conversion result; and

performing the second sampling operation of the second sample analog signal in the first A/D conversion stage, and after the first conversion operation in the second A/D conversion stage, performing the second conversion operation in the second A/D conversion stage to generate a twelfth conversion result in the second A/D conversion stage, and performing a second sampling operation of a twelfth analog signal in the third A/D conversion stage, the twelfth analog signal being associated with the twelfth conversion result.

32. The method according to claim 29, comprising the steps of:

sampling a signal to a sample/hold circuit, then holding the sampled signal in the sample/hold circuit, and generating one of the first and second sample analog signals in the sample/hold circuit, the sample/hold circuit having an operational amplification circuit; and

closing a switch connected between an input and an output of the operational amplification circuit, opening the closed switch to bring the sample/hold circuit to a holding operation stage to hold a signal, and preparing the held signal as another one of the first and second sample analog signals.

33. A method of generating a digital signal corresponding to an analog signal by using first to third AM conversion stages, each of the first to third A/D conversion stages including an operational amplification circuit, first and second capacitors and a third capacitor, each of the first and second capacitors having one terminal connected to an inverting input of the operational amplification circuit, and the third capacitor having one terminal connected to an output of the operational amplification circuit,

the method comprising the steps of:

(a) performing a first conversion operation of an analog signal sampled in the first A/D conversion stage to generate a first conversion value for the first A/D conversion stage, and after the first conversion operation in the second A/D conversion stage, performing a second conversion operation in the second A/D conversion stage to generate a second conversion value for the second A/D conversion stage, and in the third A/D conversion stage, performing a sampling operation of an analog signal associated with the second conversion value;

(b) after the first conversion operation in the first A/D conversion stage, performing a second conversion operation in the first A/D conversion stage to generate a second conversion value for the first A/D conversion stage, performing the sampling operation of an analog signal associated with the second conversion value in the second A/D conversion stage, performing the first conversion operation of an analog signal sampled in the third A/D conversion stage to generate a first conversion value for the third A/D conversion stage;

(c) performing the first conversion operation of an analog signal sampled in the second A/D conversion stage to generate a first conversion value for the second A/D conversion stage, performing the second conversion operation in the third A/D conversion stage to generate a second conversion value in the third A/D conversion stage, and in the first A/D conversion stage, performing the sampling operation of an analog signal associated with the second conversion value,

wherein the sampling operation comprises a step of storing electric charges in the first capacitor and the second capacitor, the electric charges being associated with an analog signal inputted to the relevant A/D conversion stage;

wherein the first conversion operation comprises the steps of connecting the second capacitor between the output and the inverting input of the operational amplification circuit, and supplying a conversion analog signal to the other terminal of the first capacitor to generate the first conversion value in the output of the operational amplification circuit and rearrange the electric charges in the first and second capacitors and to store an electric charge in the third capacitor, the electric charge being associated with the first conversion value, the conversion analog signal being associated with a digital signal, and the digital signal indicating an A/D conversion result in the relevant A/D conversion stage; and

the second conversion operation comprises the step of connecting the first and third capacitors between the output of the operational amplification circuit and the inverting input of the operational amplification circuit, and supplying a conversion analog signal to another terminal of the second capacitor to generate the second conversion value for the output of the operational amplification circuit and to rearrange the electric charges of the first, second and third capacitors, the conversion analog signal being associated with a digital signal, and the digital signal indicating an A/D conversion result in the relevant A/D conversion stage.

34. The method according to claim 33, further comprising a step of successively repeating the step (a) to the step (c).

35. The method according to claim 33, comprising the steps of:

prior to the steps (a) to (c), receiving a first sample analog signal in the first A/D conversion stage and performing the sampling operation with respect to the first sample analog signal;

prior to the steps (a) to (c), performing the first and second conversion operations of an analog signal sampled in the first A/D conversion stage, and, in the relevant second A/D conversion stage, performing a sampling operation of an analog signal associated with a conversion value obtained in the second conversion operation; and

prior to the steps (a) to (c), receiving a second sample analog signal in the first A/D conversion stage, performing the sampling operation of the second sample analog signal, and performing the first conversion operation of an analog signal sampled in the second A/D conversion stage.

36. The method according to claim 33, further comprising the steps of:

sampling a signal to a sample/hold circuit, then holding the sampled signal in the sample/hold circuit, and generating one of the first and second sample analog signals in the sample/hold circuit, the sample/hold circuit having an operational amplification circuit; and

closing a switch connected between an input and an output of the operational amplification circuit of the sample/hold circuit, opening the closed switch to bring the sample/hold circuit to a holding operation state to hold a signal, and preparing the held signal as another one of the first and second sample analog signals.

37. A method of generating a signal indicating a conversion error in an A/D conversion stage for generating a digital signal corresponding to an analog signal, the A/D conversion stage including first and second capacitors and an operational amplification circuit, the operational amplification circuit having an inverting input connected to one terminal of the first and second capacitors, and the conversion error being associated with mismatch in capacitance of the first and second capacitors,

the method comprising the steps of:

(a) connecting an output of the operational amplification circuit and the inverting input of the operational amplification circuit with each other and connecting another terminal of the second capacitor to a reference potential line, and applying a reference voltage to the other terminal of the first capacitor to generate a first conversion value in the output of the operational amplification circuit and arrange electric charges in the first and second capacitors; and

(b) connecting the first capacitor between an output and the inverting input of the operational amplification circuit and applying the reference voltage to the other terminal of the second capacitor to generate a second conversion value in the output of the operational amplification circuit and rearrange electric charges in the first and second capacitors.

38. A method of generating a digital signal corresponding to an analog signal by using four A/D conversion stages STG1, STG2, STG3, STG4 connected in a loop, each of these A/D conversion stages including first and second capacitors and an operational amplification circuit, the operational amplification circuit having an inverting input connected to one terminal of the first and second capacitors, and each A/D conversion stage generating a signal of a digital value in the relevant A/D conversion stage;

the method comprising the steps of;

(a) connecting another terminal of the second capacitor to a reference potential line, connecting an output of the operational amplification circuit and the inverting input of the operational amplification circuit with each other, and applying a reference voltage to another terminal of the first capacitor to arrange electric charges in the first and second capacitors of the A/D conversion stage STG1, and further performing a predetermined conversion operation of an analog signal in the A/D conversion stage STG2 to generate a conversion value in the output of the operational amplification circuit, and providing the conversion value to the A/D conversion stage STG3, and performing a predetermined sampling operation in the A/D conversion stage STG3, the conversion value corresponding to the analog signal;

(b) after the step (a), connecting the first capacitor between an output and the inverting input of the operational amplification circuit in the A/D conversion stage STG1 and applying the reference voltage to the other terminal of the second capacitor to generate a conversion value in the output of the operational amplification circuit, to supply the conversion value to the A/D conversion stage STG2 and to perform the predetermined sampling operation in the A/D conversion stage STG2,

performing the predetermined conversion operation of a signal sampled in the A/D conversion stage STG3 to generate a conversion value in the output of the operational amplification circuit, supplying this conversion value to the A/D conversion stage STG4 to perform the predetermined sampling operation in the A/D conversion stage STG4, the conversion value being associated with the sampled signal;

(c) performing the predetermined conversion operation of a signal sampled in the A/D conversion stage STG2 to generate a conversion value in the output of the operational amplification circuit, and supplying this conversion value to the A/D conversion stage STG3, the conversion value being associated with the sampled signal,

performing the predetermined sampling operation in the A/D conversion stage STG3, then performing the predetermined conversion operation of a signal sampled in the A/D conversion stage STG4 to generate a conversion value in the output of the operational amplification circuit, and supplying this conversion value to the A/D conversion stage STG1 to perform the predetermined sampling operation in the A/D conversion stage STG1, the conversion value being associated with the sampled signal; and

(d) performing the predetermined conversion operation of a signal sampled in the A/D conversion stage STG3 to generate a conversion value in the output of the operational amplification circuit, supplying this conversion value to the A/D conversion stage STG4 to perform the predetermined sampling operation in the A/D conversion stage STG4, the conversion value being associated with the sampled signal,

then performing the predetermined conversion operation of a signal sampled in the A/D conversion stage STG1 to generate a conversion value in the output of the operational amplification circuit, supplying this conversion value to the A/D conversion stage STG2 to perform a predetermined sampling operation in the A/D conversion stage STG2, the conversion value being associated with the sampled signal,

wherein the predetermined sampling operation comprises the step of storing electric charges in the first capacitor and the second capacitor, the electric charges corresponding to an input analog signal; and

wherein the predetermined conversion operation comprises the step of connecting the first capacitor between an output of the operational amplification circuit and an inverting input of the operational amplification circuit, and supplying a conversion analog signal to another terminal of the second capacitor to generate a conversion value in the output of the operational amplification circuit and rearrange the electric charges of the first and second capacitor, the conversion analog signal being associated with a digital signal, and the digital signal indicating an A/D conversion result in the A/D conversion stage.

39. The method according to claim 38, wherein a sample/hold circuit is connected to an input of any one A/D conversion stage from among the A/D conversion stages STG1 to STG4;

and the analog signal in the step (a) is associated with a sample analog signal.

40. A method of generating a signal indicating a conversion error in an A/D conversion stage for generating a digital signal corresponding to an analog signal, the A/D conversion stage including first and second capacitors and an operational amplification circuit, the operational amplification circuit having an inverting input connected to one terminal of the first and second capacitors, and the conversion error includes a finite gain error due to a finite gain of the operational amplification circuit,

the method comprising the steps of:

(a) connecting an output of the operational amplification circuit and the inverting input of the operational amplification circuit with each other and applying a reference voltage to another terminal of the second capacitor to another terminal of the first capacitor to generate a first conversion value in the output of the operational amplification circuit and to arrange electric charges in the first and second capacitors; and

(b) connecting the first capacitor between an output of the operational amplification circuit and the inverting input of the operational amplification circuit, and applying the reference voltage to the other terminal of the second capacitor to generate a second conversion value in the output of the operational amplification circuit and to rearrange electric charges in the first and second capacitors.

41. A method of generating a digital signal corresponding to an analog signal by using four A/D conversion stages STG1, STG2, STG3, STG4 connected in a loop, each of these A/D conversion stages including first and second capacitors and an operational amplification circuit, the operational amplification circuit having an inverting input connected to one terminal of the first and second capacitors, and each A/D conversion stage generating a signal of a digital value of the relevant A/D conversion stage;

the method comprising the steps of;

(a) connecting an output of the operational amplification circuit and the inverting input of the operational amplification circuit with each other and applying a reference voltage to another terminal of the second capacitor and another terminal of the first capacitor to arrange electric charges in the first and second capacitors in the A/D conversion stage STG1, and

further performing a predetermined conversion operation of an analog signal in the A/D conversion stage STG2 to generate a conversion value in the output of the operational amplification circuit, supplying this conversion value to the A/D conversion stage STG3 to perform a predetermined sampling operation in the A/D conversion stage STG3, the conversion value corresponding to the analog signal;

(b) after the step (a), connecting the first capacitor between an output and the inverting input of the operational amplification circuit in the A/D conversion stage STG1 and applying the reference voltage to the other terminal of the second capacitor to generate a conversion value in the output of the operational amplification circuit, to supply the conversion value to the A/D conversion stage STG2, and to perform the predetermined sampling operation in the A/D conversion stage STG2, and

further performing the predetermined conversion operation of a signal sampled in the A/D conversion stage STG3 to generate a conversion value, providing this conversion value to the A/D conversion stage STG4, and performing the predetermined sampling operation in the A/D conversion stage STG4, the conversion value being associated with the sampled signal for the output of the operational amplification circuit;

(c) performing the predetermined conversion operation of a signal sampled in the A/D conversion stage STG2 to generate a conversion value in the output of the operational amplification circuit, and supplying this conversion value to the A/D conversion stage STG3 to perform the predetermined sampling operation in the A/D conversion stage STG3, the conversion value being associated with a sampled signal, and

performing the predetermined conversion operation of a signal sampled in the A/D conversion stage STG4 to generate a conversion value in the output of the operational amplification circuit, and supplying this conversion value to the A/D conversion stage STG1 to perform the predetermined sampling operation in the A/D conversion stage STG1, the conversion value being associated with a sampled signal; and

(d) performing the predetermined conversion operation of a signal sampled in the A/D conversion stage STG3 to generate a conversion value in the output of the operational amplification circuit, supplying this conversion value to the A/D conversion stage STG4 to perform the predetermined sampling operation in the A/D conversion stage STG4, the conversion value being associated with the sampled signal, and

performing the predetermined conversion operation of a signal sampled in the A/D conversion stage STG1 to generate a conversion value in the output of the operational amplification circuit, supplying this conversion value to the A/D conversion stage STG2 to perform the predetermined sampling operation in the A/D conversion stage STG2, the conversion value being associated with the sampled signal,

wherein the predetermined sampling operation comprises the step of storing an electric charge in the first capacitor and the second capacitor, the electric charge being associated with an input analog signal; and

wherein the predetermined conversion operation comprises the step of connecting the first capacitor between an output of the operational amplification circuit and an inverting input of the operational amplification circuit, and supplying a conversion analog signal to the other terminal of the second capacitor to generate a conversion value in the output of the operational amplification circuit and to rearrange the electric charges of the first and second capacitors, the conversion analog signal being associated with a digital signal, and the digital signal indicating an A/D conversion result in the relevant A/D conversion stage.

42. The method according to claim 41, wherein a sample/hold circuit is connected to an input of any one of A/D conversion stage from among the A/D conversion stages STG1 to STG4;

and the analog signal in the step (a) is associated with a sample analog signal.