High-speed controller for phase-change memory peripheral device

• US 7,889,544 B2
• Filed: 06/28/2007
• Issued: 02/15/2011
• Est. Priority Date: 04/05/2004
• Status: Expired due to Fees

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Yu, Frank I-Kang, Lee, Charles C., Chow, David Q.
• Primary Examiner(s): Ho; Hoai V
• Assistant Examiner(s): Lappas; Jason
• Application Number:
  US11/770,642
• Publication Number:
  US 20070255891A1
• Time in Patent Office: 1,328 Days
• Field of Search: 365/163, 365/230.03, 365/189.01, 365/148
• US Class Current: 365/163
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0071 Write using write potential applied to access device gate
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1015 Read-write modes for single port memories, i.e. having either a random port or a serial port
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

Peripheral devices store data in non-volatile phase-change memory (PCM). PCM cells have alloy resistors with high-resistance amorphous states and low-resistance crystalline states. The peripheral device can be a Multi-Media Card/Secure Digital (MMC/SD) card. A PCM controller accesses PCM memory devices. Various routines that execute on a CPU in the PCM controller are activated in response to commands in the host-bus transactions. The PCM system increases the throughput of one or more phase-change memory devices by performing one or more of a read-ahead memory operation, a write-ahead memory write operation, a larger page memory write operation, a wider data bus memory write operation, a multi-channel concurrent multi-bank interleaving memory read or write operation, a write-cache memory write operation, and any combination thereof.

Claims

1. A phase-change-memory peripheral comprising:

a peripheral phase-change-memory controller having a central processing unit (CPU) for executing instructions and a random-access memory (RAM) for storing instructions for execution by the CPU;

throughput-increasing control routines of instructions executed by the CPU, wherein the throughput-increasing control routines increase a throughput of the phase-change-memory peripheral by performing one or more of a read-ahead memory operation, a write-ahead memory write operation, a larger page memory write operation, a wider data bus memory write operation, a dual-channel concurrent memory read operation, a dual-channel concurrent memory write operation, a write-cache memory write operation, a multi-channel concurrent multi-bank memory read operation, a multi-channel concurrent multi-bank memory write operation, a multi-channel concurrent multi-bank memory write cache operation;

a bus transceiver in the peripheral phase-change-memory controller for receiving peripheral commands and data from a host over a host bus;

a phase-change-memory controller in the peripheral phase-change-memory controller;

a plurality of phase-change memory (PCM) cells organized as phase-change-memory mass storage devices, coupled to the phase-change-memory controller, for storing non-volatile data for the host, the data in the phase-change-memory mass storage devices being block-addressable and not randomly-addressable;

wherein each PCM cell in the plurality of PCM cells has a first logical state having an alloy in a crystalline phase and a second logical state having the alloy in an amorphous phase, wherein a resistance of the alloy is higher when in the amorphous phase than when in the crystalline phase; and

a phase-change-memory bus having data lines for transferring data from the phase-change-memory controller to the phase-change-memory mass storage devices,

whereby the peripheral phase-change-memory controller controls the phase-change-memory mass storage devices that are block-addressable.

2. The phase-change-memory peripheral of claim 1 wherein a PCM cell in the plurality of PCM cells comprises:

a select transistor receiving a word line on a gate, and having a channel between a bit line and a cell node;

an alloy resistor formed from the alloy, coupled between the cell node and an array voltage;

wherein the PCM cell has the first logical state when the alloy resistor has the alloy in the crystalline phase, the alloy resistor having a low resistance that increases a sensing current from the bit line through the select transistor;

wherein the PCM cell has the second logical state when the alloy resistor has the alloy in the amorphous phase, the alloy resistor having a high resistance that reduces the sensing current from the bit line through the select transistor;

wherein the high resistance is larger than the low resistance;

whereby the sensing current is altered by the alloy being in the crystalline phase and the amorphous phase.

3. The phase-change-memory peripheral of claim 2 further comprising write drivers which comprise:

a set current generator, coupled to the bit line, for driving a set current through the select transistor and through the alloy resistor for a set period of time to write the PCM cell into the first logical state in response to set data bits in the data;

a reset current generator, coupled to the bit line, for driving a reset current through the select transistor and through the alloy resistor for a reset period of time to write the PCM cell into the second logical state in response to reset data bits in the data;

a reset timer for determining the reset period of time; and

a set timer for determining the set period of time;

wherein the set period of time is at least double the reset period of time,

whereby the PCM cell is set for a longer time period, and reset for a shorter time period.

4. The phase-change-memory peripheral of claim 3 wherein the reset current is at least twice the set current, and wherein the set current is at least twice the sensing current;

whereby the PCM cell is set by a lower current for a longer time period, and reset by a higher current and a shorter time period.

5. The phase-change-memory peripheral of claim 4 wherein the alloy is a chalcogenide glass layer having a melting point that is higher than a crystallization point.

6. The phase-change-memory peripheral of claim 5 wherein the alloy is an alloy of germanium (Ge), antimony (Sb), and tellurium (Te).

7. The phase-change-memory peripheral of claim 1 wherein the PCM cells are organized into banks that are concurrently writable, further comprising:

local bank write latches, storing write data that includes set data bits indicating the first logical state and reset data bits indicating the second logical state, the local bank write latches coupled to control local write drivers to drive the set pulse and the reset pulse to the selected PCM cells.

8. The phase-change-memory peripheral of claim 2 wherein the bus transceiver connects to the host bus which is a Multi-Media Card/Secure Digital (MMC/SD) bus, an integrated device electronics (IDE) bus, an AT-Attachment (ATA) bus, a CompactFlash (CF) bus, a Memory Stick (MS) interface bus, a Serial AT-Attachment (SATA) bus, a Small Computer System Interface (SCSI) bus, or a PCI-Express (PCIe) interface bus.

9. A phase-change-memory solid-state-storage device comprising:

host interface means for connecting to a host over a host bus;

a phase-change-memory controller having a processor for executing instructions;

a main memory coupled to the processor for storing instructions for execution by the processor;

phase-change memory means for storing a data word as binary bits each represented by a chalcogenide glass layer having a melting point that is higher than a crystallization point, the chalcogenide glass layer forming a variable resistor that alters a sensing current when a binary bit is read;

wherein a crystalline state of the variable resistor represents a first binary logic state and an amorphous state of the variable resistor represents a second binary logic state for binary bits stored in the phase-change memory means;

phase-change-memory controller means for controlling access of the phase-change memory means; and

throughput-increasing control routine means for execution by the processor, wherein the throughput-increasing control routine means is for increasing a throughput of the phase-change-memory controller.

10. The phase-change-memory solid-state-storage device of claim 9 wherein the throughput-increasing control routine means comprises at least one of:

read-ahead memory operation means for performing a read-ahead memory operation on the phase-change memory means;

write-ahead memory write operation means for performing a write-ahead memory operation on the phase-change memory means;

dual-channel concurrent read memory operation means for performing a dual-channel concurrent read memory operation on the phase-change memory means;

dual-channel concurrent write memory operation means for performing a dual-channel concurrent write memory operation on the phase-change memory means;

write-cache memory operation means for performing a write-cache memory operation on the phase-change memory means;

multi-channel concurrent multi-bank interleaved read-ahead memory operation means for performing a read-ahead memory operation on multiple interleaved banks of the phase-change memory means using multiple channels; and

multi-channel concurrent multi-bank interleaved write-ahead memory operation means for performing a write-ahead memory operation on multiple interleaved banks of the phase-change memory means using multiple channels.

11. The phase-change-memory solid-state-storage device of claim 10 further comprising:

address translation means for translating block addresses from the processor to access the phase-change memory means as data blocks having multiple data words; and

direct-memory access (DMA) engine means for directly transferring data and instructions over an internal bus among the host interface, the main memory, the processor, and the phase-change-memory controller means,

whereby data blocks are accessed in the phase-change memory means.

12. The phase-change-memory solid-state-storage device of claim 11 wherein the host interface comprises:

host transceiver means for receiving clocked data and commands from the host bus, and for driving data onto the host bus in response to a command;

host operating register means for storing data and commands in a format specified by a host protocol specification; and

command decoder and validator means, coupled to the host operating register means, for decoding and validating a command received over the host bus by the host transceiver means.

13. The phase-change-memory solid-state-storage device of claim 12 wherein the host bus is a Multi-Media Card/Secure Digital (MMC/SD) bus, an integrated device electronics (IDE) bus, an AT-Attachment (ATA) bus, a CompactFlash (CF) bus, a Memory Stick (MS) interface bus, a Serial AT-Attachment (SATA) bus, a Small Computer System Interface (SCSI) bus, or a PCI-Express (PCIe) interface bus.

14. The phase-change-memory solid-state-storage device of claim 10 wherein the phase-change-memory controller means further comprises:

a first channel for connecting to a first section of the phase-change memory means, the first channel comprising;

first PCM interface control registers for storing control information for controlling operation of the first section of the phase-change memory means;

first sector buffers for storing a first block of data for writing to the first section of the phase-change memory means;

first PCM DMA engine means for transferring the first block of data from the first sector buffers to the first section of the phase-change memory means;

a second channel for connecting to a second section of the phase-change memory means, the second channel comprising;

second PCM interface control registers for storing control information for controlling operation of the second section of the phase-change memory means;

second sector buffers for storing a second block of data for writing to the second section of the phase-change memory means; and

second PCM DMA engine means for transferring the second block of data from the second sector buffers to the second section of the phase-change memory means,

whereby the phase-change-memory controller means has multiple channels to access the phase-change memory means.

15. A phase-change-memory peripheral system comprising:

a clocked-data interface to a host bus that connects to a host;

a bus transceiver for detecting and processing commands sent over the host bus;

a buffer for storing data sent over the host bus;

an internal bus coupled to the buffer;

a random-access memory (RAM) for storing instructions for execution, the RAM on the internal bus;

a central processing unit, on the internal bus, the CPU accessing and executing instructions in the RAM;

a phase-change-memory controller, on the internal bus, for generating phase-change-memory-control signals and for buffering data to a phase-change-memory bus;

phase-change-memory devices coupled to the phase-change-memory controller by the phase-change-memory bus, and controlled by the phase-change-memory-control signals;

a direct-memory access (DMA) engine, on the internal bus, for transferring data over the internal bus;

wherein the phase-change-memory devices comprise an array of memory cells;

an alloy resistor in each memory cell in the array of memory cells, the alloy resistor storing binary data as solid phases each having a different resistivity;

wherein the alloy resistor changes from a crystalline state to an amorphous state when a memory cell is written from a logic 1 state to a logic 0 state in response to a reset current for a reset period of time;

wherein the alloy resistor changes from the amorphous state to the crystalline state when the memory cell is written from a logic 0 state to a logic 1 state in response to a set current for a set period of time;

wherein the amorphous state has a higher resistance than the crystalline state that is sensed by a sense amplifier; and

a plurality of write drivers that apply the set current for the set period of time to memory cells being written by bits in the logic 1 state, and apply the reset current for the reset period of time to memory cells being written by bits in the logic 0 state,

whereby data from the host is stored by the crystalline state and the amorphous state of the alloy resistor in each memory cell.

16. The phase-change-memory peripheral system of claim 15 further comprising:

throughput-increasing control routines of instructions for execution by the CPU, wherein the throughput-increasing control routines increase a throughput of the phase-change-memory controller.

17. The phase-change-memory peripheral system of claim 16 wherein the phase-change-memory devices further comprise:

a plurality of banks of memory cells, each bank in the plurality of banks having an array of memory cells;

a data input for receiving a data word to store in the phase-change memory;

a write buffer, coupled to the data input to receive the data word;

data lines coupled between the write buffer and the plurality of banks of memory cells, for transferring the data word to the plurality of banks;

a plurality of bank write latches, wherein each bank in the plurality of banks has a local bank write latch that receives a bank portion of the data word from the data lines;

wherein the plurality of write drivers comprise, for each bank in the plurality of banks, a local write driver that applies the set current for the set period of time to memory cells being written by bits in the logic 1 state in the bank portion of the data word stored in the local bank write latches, and that applies the reset current for the reset period of time to memory cells being written by bits in the logic 0 state in the bank portion of the data word stored in the local bank write latches;

wherein the set period of time is at least 5 times longer than the reset period of time;

wherein unequal set and reset pulses are applied to the alloy resistors to for changes between the crystalline state and the amorphous state; and

a plurality of bank sense amplifiers, wherein each bank in the plurality of banks has a local bank sense amplifier that senses data stored in selected memory cells by sensing currents passing through alloy resistors having a higher resistance when in the amorphous state than when in the crystalline state;

wherein the bank portion of the data word is written from the local bank write latches into the memory cells while the data lines are disconnected from writing the local bank write latches, the data lines able to transfer data to other banks in the plurality of banks while the data word is written from the local bank write latches into the memory cells,

whereby concurrent writes and data transfers to different banks are performed.

18. The phase-change-memory peripheral system of claim 17 wherein the set period of time is about 100 nanoseconds.

19. The phase-change-memory peripheral system of claim 17 wherein the data word stored in the memory cells is retained when power is disconnected,

wherein the alloy resistors remain in the amorphous state and remain in the crystalline state when power is disconnected;

whereby the data word is stored in non-volatile memory.

20. The phase-change-memory peripheral system of claim 17 wherein the throughput-increasing control routines comprise at least one of:

read-ahead memory operation means for performing a read-ahead memory operation on the phase-change memory devices;

write-ahead memory write operation means for performing a write-ahead memory operation on the phase-change memory devices;

dual-channel concurrent read memory operation means for performing a dual-channel concurrent read memory operation on the phase-change memory devices;

dual-channel concurrent write memory operation means for performing a dual-channel concurrent write memory operation on the phase-change memory devices; and

write-cache memory operation means for performing a write-cache memory operation on the phase-change memory devices.