Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks

• US 7,889,554 B2
• Filed: 11/23/2009
• Issued: 02/15/2011
• Est. Priority Date: 02/17/2000
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Conley, Kevin M., Mangan, John S., Craig, Jeffrey G.
• Primary Examiner(s): CHAN, WING F
• Application Number:
  US12/624,258
• Publication Number:
  US 20100067298A1
• Time in Patent Office: 449 Days
• Field of Search: 365/185.11, 365/230.06, 365/189.05
• US Class Current: 365/185.11
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities.

Claims

1. In a memory system including re-programmable non-volatile memory cells organized into distinct blocks of a minimum number of memory cells that are simultaneously erasable and a buffer memory, the blocks of memory cells being further organized into a plurality of sub-arrays that individually have at least one storage register associated therewith, a method of operating the system, comprising:

receiving user data to be programmed into the memory system and temporarily storing the received user data in the buffer memory,

transferring user data from the buffer memory to the storage registers, a portion of the user data stored in the buffer memory being moved into one of the storage registers at a time,

storing in at least one of the blocks a record of the individual blocks that are identified for storing user data that includes logical addresses assigned to the individual blocks identified for storing user data,

accessing the record in response to receiving logical addresses by determining the physical addresses that correspond with the received logical addresses,

programming user data in parallel from their associated storage registers into a plurality of physical blocks within a plurality of sub-arrays in response to receiving logical addresses; and

storing, in at least one other block different than the blocks identified for storing user data, information of physical characteristics of the blocks identified to store user data or their operation.

2. The method of claim 1, wherein the numbers of blocks identified for storing user data in individual ones of the plurality of sub-arrays are different.

3. The method of claim 1, wherein programming user data additionally comprises reading the information of physical characteristics of the blocks being accessed to store user data or their operation and using the read information to set parameters used to program the user data in the blocks being accessed.

4. The method of claim 1, additionally comprising reading user data programmed into blocks identified for storing user data by accessing the physical blocks through logical addresses, including reading the information of physical characteristics of the blocks being accessed or their operation and using the read information to set parameters used to read the user data from the blocks being accessed.

5. The method of claim 1, wherein storing information of physical characteristics of blocks identified to store user data or their operation comprises storing an indication of whether any of the blocks identified to store user data is defective.

6. The method of claim 5, wherein if any of the blocks identified to store user data is defective, storing information of the physical characteristics of the defective block or its operation additionally comprises storing an address of another of the blocks identified to store user data as a substitute for the defective block.

7. The method of claim 5, wherein storing data of information related to physical characteristics of the blocks identified to store user data or their operation additionally comprises storing any of programming, reading, erase or wear characteristics of the blocks identified to store user data.

8. The method of any one of claims 1-7, wherein the memory cells within at least the blocks identified for storing user data are individually operated with more than two storage states in order to store more than one bit of user data per memory cell.