Nonvolatile semiconductor memory device in which an amount of data to be stored in a memory cell is allocated to every other word line units of one word line

• US 7,889,558 B2
• Filed: 02/08/2008
• Issued: 02/15/2011
• Est. Priority Date: 02/09/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kanda, Kazushige
• Primary Examiner(s): Ho; Hoai V
• Application Number:
  US12/028,480
• Publication Number:
  US 20080205148A1
• Time in Patent Office: 1,103 Days
• Field of Search: 365/94, 365/185.03, 365/185.17, 365/185.21, 365/185.28
• US Class Current: 365/185.17
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A nonvolatile semiconductor memory device having a plurality of word lines and a plurality of bit lines and a plurality of sense amplifiers, each amplifier being connected to one of the plurality of bit lines respectively and a memory cell array including a memory cell region including a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, each of the memory cells having two or more storage states, said plurality of memory cells being connected to a corresponding word line of the plurality of word lines respectively, the plurality of memory strings being connected to a corresponding bit line of the plurality of bit lines respectively, and at the time of programming all of the plurality of bit lines are selected, the number of the storage states being different in two of the memory cells which are adjacent on the same bit line.

Claims

1. A nonvolatile semiconductor memory device comprising:

a plurality of word lines;

a plurality of bit lines;

a plurality of sense amplifiers, each amplifier being connected to one of said plurality of bit lines respectively; and

a memory cell array including a memory cell region including a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, each cell of said plurality of memory cells having two or more storage states, said plurality of memory cells being connected to a corresponding word line of said plurality of word lines respectively, said plurality of memory strings being connected to a corresponding bit line of said plurality of bit lines respectively, and at the time of programming, the number of said storage states being different in two of said memory cells, one of said two memory cells being arranged in the middle of a series of three memory cells of said plurality of memory cells connected in series to the same bit line, and the other memory cell of said two memory cells being adjacent to the middle memory cell.

2. The nonvolatile semiconductor memory device according to claim 1, said each sense amplifier further comprising:

a storage states change circuit which changes said storage states of said memory cell transistors respectively by an external input.

3. The nonvolatile semiconductor memory device according to claim 1, wherein,

said each sense amplifier further comprises a storage states change circuit which changes said storage states of said memory cell transistors respectively,

said memory cell array further including a ROM region, and

the number of said storage states of said memory cell transistors are stored in said ROM region.

4. The nonvolatile semiconductor memory device according to claim 1, said nonvolatile semiconductor memory device further comprising:

a power on reset circuit having at least two internal fuse circuits which store the number of said storage states of said memory cell transistors according to a corresponding address of said memory cell transistors, the number of said storage states being changed according to the number of said storage states stored in either of said two internal fuse circuits at the time of resetting said nonvolatile semiconductor memory device.

5. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is a NAND type flash memory.

6. The nonvolatile semiconductor memory device according to claim 1, wherein each of said storage states is 2ⁿ (n is a natural number).

7. The nonvolatile semiconductor memory device according to claim 1, further comprising a group of four memory cells connected in series to the same bit line wherein the number of storage states in the first and third memory cells is different to the number of storage states in the second and fourth memory cells.

8. The nonvolatile semiconductor memory device according to claim 1, wherein the amount of storage states to be stored in a memory cell is allocated to every other word line in units of one word line.

9. A nonvolatile semiconductor memory device comprising:

a plurality of word lines having odd word lines and even word lines;

a plurality of bit lines;

a plurality of sense amplifiers, each amplifier being connected to one of said plurality of bit lines respectively; and

a memory cell array including a memory cell region including a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, each memory cell of said plurality of memory cells having two or more storage states, said plurality of memory cells being connected to a corresponding word line of said plurality of word lines respectively, said plurality of memory strings being connected to a corresponding bit line of said plurality of bit lines respectively, at the time of programming , the number of said storage states of said memory cells connected to said odd word lines is different from the number of said storage states of said memory cells connected to said even word lines, and the number of said storage states being different in two of said memory cells, one of said two memory cells being arranged in the middle of a series of three memory cells of said plurality of memory cells connected in series to the same bit line, and the other memory cell of said two memory cells being adjacent to the middle memory cell.

10. The nonvolatile semiconductor memory device according to claim 9, said each sense amplifier further comprising:

a storage states change circuit which changes said storage states of said memory cell transistors respectively by an external input.

11. The nonvolatile semiconductor memory device according to claim 9, wherein,

said each sense amplifier further comprises a storage states change circuit which changes said storage states of said memory cell transistors respectively,

said memory cell array further including a ROM region, and

the number of said storage states of said memory cell transistors are stored in said ROM region.

12. The nonvolatile semiconductor memory device according to claim 9, said nonvolatile semiconductor memory device further comprising:

a power on reset circuit having at least two internal fuse circuits which store the number of said storage states of said memory cell transistors according to a corresponding address of said memory cell transistors, the number of said storage states being changed according to the number of said storage states stored in either of said two internal fuse circuits at the time of resetting said nonvolatile semiconductor memory device.

13. The nonvolatile semiconductor memory device according to claim 9, wherein the nonvolatile semiconductor memory device is a NAND type flash memory.

14. The nonvolatile semiconductor memory device according to claim 9, further comprising a group of four memory cells connected in series to the same bit line wherein the number of storage states in the first and third memory cells is different to the number of storage states in the second and fourth memory cells.

15. The nonvolatile semiconductor memory device according to claim 9,

wherein the amount of storage states to be stored in a memory cell is allocated to every other word line in units of one word line.

16. A nonvolatile semiconductor memory device comprising:

a plurality of word lines;

a plurality of bit lines;

a plurality of sense amplifiers, each amplifier being connected to one of said plurality of bit lines respectively; and

a memory cell array including a memory cell region including a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, each memory cell of said plurality of memory cells having two or more storage states, said plurality of memory cells being connected to a corresponding word line of said plurality of word lines respectively, said plurality of memory strings being connected to a corresponding bit line of said plurality of bit lines respectively, each of first addresses being allocated to one of said plurality of said memory cells, each of second addresses being allocated to two of said plurality of memory cells which are adjacent on the same bit line, said two of said plurality of memory cells being selected by a corresponding first address of said first addresses and a corresponding second address of said second addresses, and at the time of programming , the number of said storage states being different in two of said memory cells, one of said two memory cells being arranged in the middle of a series of three memory cells of said plurality of memory cells connected in series to the same bit line, and the other memory cell of said two memory cells being adjacent to the middle memory cell.

17. The nonvolatile semiconductor memory device according to claim 16, said each sense amplifier further comprising:

a storage states change circuit which changes said storage states of said memory cell transistors respectively by an external input.

18. The nonvolatile semiconductor memory device according to claim 16, wherein,

said each sense amplifier further comprises a storage states change circuit which changes said storage states of said memory cell transistors respectively,

said memory cell array further including a ROM region, and

the number of said storage states of said memory cell transistors are stored in said ROM region.

19. The nonvolatile semiconductor memory device according to claim 16, said nonvolatile semiconductor memory device further comprising:

a power on reset circuit having at least two internal fuse circuits which store the number of said storage states of said memory cell transistors according to a corresponding address of said memory cell transistors, the number of said storage states being changed according to the number of said storage states stored in either of said two internal fuse circuits at the time of resetting said nonvolatile semiconductor memory device.

20. The nonvolatile semiconductor memory device according to claim 16, said nonvolatile semiconductor memory device further comprising:

a calculation circuit which converts one of said first addresses into a corresponding second address of said second addresses and one of said second addresses into a corresponding first address of said first addresses.

21. The nonvolatile semiconductor memory device according to claim 20, said nonvolatile semiconductor memory device further comprising:

a plurality of latch circuits, each of said plurality of latch circuits being connected to a corresponding sense amplifier of said plurality of sense amplifiers, a first data and a second data being stored in said two of said plurality of memory cells which are adjacent on the same bit line respectively, said first data corresponding to said second address being read and latched in a corresponding latch circuit, said second data corresponding to said second address being read, and said first data latched in said corresponding latch circuit and said second data being logically operated and output as a data of said second address.

22. The nonvolatile semiconductor memory device according to claim 16, wherein the nonvolatile semiconductor memory device is a NAND type flash memory.

23. The nonvolatile semiconductor memory device according to claim 16, further comprising a group of four memory cells connected in series to the same bit line wherein the number of storage states in the first and third memory cells is different to the number of storage states in the second and fourth memory cells.

24. The nonvolatile semiconductor memory device according to claim 16, wherein the amount of storage states to be stored in a memory cell is allocated to every other word line in units of one word line.