Semiconductor memory device employing clamp for preventing latch up

• US 7,889,574 B2
• Filed: 07/24/2008
• Issued: 02/15/2011
• Est. Priority Date: 04/27/2004
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Byeon, Sang-Jin, Lee, Kang-Seol
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US12/219,572
• Publication Number:
  US 20080285356A1
• Time in Patent Office: 936 Days
• Field of Search: 365/189.06, 365/189.09, 365/203, 365/204
• US Class Current: 365/189.06
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A semiconductor memory device employs a clamp for preventing latch up. For the purpose, the semiconductor memory device includes a precharging/equalizing unit for precharging and equalizing a pair of bit lines, and a control signal generating unit for producing a control signal which controls enable and disable of the precharging/equalizing unit, wherein the control signal generating unit includes a clamping unit to clamp its source voltage to a voltage level lower than that of its bulk bias.

Claims

1. A semiconductor memory device, comprising:

a pair of data lines;

a first driving unit comprising a first CMOS transistor, configured to drive an input signal to one of the pair of data lines;

a second driving unit comprising a second CMOS transistor, configured to drive an input signal to the other data line;

a precharging/equalizing unit comprising at least two MOS transistors, configured to precharge and equalize the pair of data lines;

a first clamping unit configured to supply a source voltage of the first CMOS transistor in response to a bulk bias voltage of the first CMOS transistor;

a second clamping unit configured to supply a source voltage of the second CMOS transistor in response to a bulk bias voltage of the second CMOS transistor; and

a third clamping unit configured to supply a source voltage of the two MOS transistors in response to a bulk bias voltage of the two MOS transistor.

2. The semiconductor memory device of claim 1, wherein the first, second and third clamping units include an NMOS transistor configured respectively to output the source voltages through a drain thereof in response to the bulk bias voltages input though a gate thereof.

3. The semiconductor memory device of claim 2, wherein the NMOS transistor of which a source is provided with a supply voltage and a gate is coupled with a voltage boosted from the supply voltage, and which receives a voltage reduced from a ground voltage as a bulk bias.

4. The semiconductor memory device of claim 1, wherein the first, second and third clamping units include a PMOS transistor configured respectively to output the source voltages through a drain thereof in response to the bulk bias voltages input though a gate thereof.

5. The semiconductor memory device of claim 4, wherein the PMOS transistor of which a source is provided with a ground voltage and a gate is coupled with a voltage reduced from the ground voltage, and which receives a voltage boosted from a supply voltage as a bulk bias.

6. A semiconductor memory device, comprising:

a CMOS transistor configured to includes a PMOS transistor and an NMOS transistor; and

a clamping unit configured to supply a source voltage of the CMOS transistor in response to a bulk bias voltage of the CMOS transistor,

wherein the PMOS transistor and the NMOS transistor have gates commonly forming an input node and drains commonly forming an output node of the CMOS transistor, the PMOS transistor uses a boosted voltage as a bulk bias, and the NMOS transistor uses a reduced voltage as a bulk bias.

7. The semiconductor memory device of claim 6, wherein the clamping unit includes an NMOS transistor of which an output voltage is output as a source voltage of the PMOS transistor through a drain thereof in response to a bulk bias voltage of the PMOS transistor input though a gate thereof.

8. The semiconductor memory device of claim 7, wherein the NMOS transistor of which a source is provided with a supply voltage and a gate is coupled with the boosted voltage, and which receives the reduced voltage as a bulk bias.

9. The semiconductor memory device of claim 6, wherein the clamping unit includes a PMOS transistor of which an output voltage is output as a source voltages of the NMOS transistor through a drain thereof in response to a bulk bias voltage of the NMOS transistor input though a gate thereof.

10. The semiconductor memory device of claim 9, wherein the PMOS transistor of which a source is provided with a ground voltage and a gate is coupled with the reduced voltage, and which receives the boosted voltage as a bulk bias.