Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks

• US 7,889,590 B2
• Filed: 11/03/2009
• Issued: 02/15/2011
• Est. Priority Date: 02/17/2000
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Conley, Kevin M., Mangan, John S., Craig, Jeffrey G.
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US12/611,280
• Publication Number:
  US 20100049910A1
• Time in Patent Office: 469 Days
• Field of Search: 365/230.03, 365/185.11
• US Class Current: 365/230.03
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities.

Claims

1. A method of operating a memory system having an array of re-programmable non-volatile memory cells organized into distinct blocks of a plurality of simultaneously erasable memory cells that are capable of storing a given quantity of data, comprising:

utilizing a map of logical block addresses into corresponding physical addresses of the blocks that groups the logical block addresses into a plurality of distinct non-overlapping ranges of continuous logical block addresses; and

accessing at least one of the physical blocks in response to a logical block address received by the memory system by identifying at least one of the plurality of ranges in which the received logical block address exists and the physical address of the block being accessed that corresponds to the received logical block address within the identified range.

2. The method of claim 1, wherein utilizing the map additionally includes identifying those of the blocks designated to store user data.

3. The method of claim 1, wherein the memory system in which the method is carried out has its blocks organized in a plurality of sub-arrays, and wherein the plurality of ranges of logical block addresses individually include a range of logical block addresses that correspond to addresses of physical blocks within less than all of the plurality of sub-arrays.

4. The method of claim 3, wherein the less than all of the plurality of sub-arrays are accessed on one integrated circuit chip.

5. The method of claim 3, wherein the less than all of the plurality of sub-arrays are accessed on more than one integrated circuit chip.

6. The method of any one of claims 1-5, wherein numbers of logical block addresses within at least two of said ranges of logical block addresses are different.

7. The method of claim 6, additionally comprising accessing another of the physical blocks not designated to store user data by identifying a corresponding another logical block address, wherein said another logical block address is absent from said ranges of logical block addresses, for storing data of parameters used to operate the memory system.

8. The method of claim 2, additionally comprising accessing another physical block not designated to store user data by identifying a corresponding another logical block address, wherein said another logical block address is absent from said ranges of logical block addresses, for storing data of parameters used to operate the memory system.

9. The method of any one of claims 1-5 and 8, wherein the memory cells of at least some of the physical blocks of memory cells are individually operated with more than two storage states in order to store more than one bit of data per memory cell.

10. The method of any one of claims 1,3,4,5 and 8, additionally comprising simultaneously programming user data into a plurality of physical blocks.

11. The method of claim 10, wherein logical block addresses corresponding to the plurality of physical blocks are within different ones of the plurality of ranges of logical block addresses.

12. The method of any one of claims 1-5 and 8, wherein the memory system in which the method of operation is carried out is contained within an enclosed memory card having electrical contacts thereon that match electrical contacts of a receptacle of a host system, the memory card thereby being removably connectable with the host system.