Systems, methods, and apparatuses for complementary metal oxide semiconductor (CMOS) antenna switches using body switching in multistacking structure

• US 7,890,063 B2
• Filed: 09/18/2007
• Issued: 02/15/2011
• Est. Priority Date: 10/03/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd., Georgia Tech Research Corporation (University System of Georgia)
• Original Assignee: Samsung Electronics Co. Ltd., Georgia Tech Research Corporation (University System of Georgia)
• Inventors: Cho, Changhyuk, Woo, Wangmyong, Ahn, Minsik, Lee, Chang-Ho, Chang, Jaejoon, Kim, Haksun, Laskar, Joy
• Primary Examiner(s): Yun; Eugene
• Application Number:
  US11/857,322
• Publication Number:
  US 20080079653A1
• Time in Patent Office: 1,246 Days
• Field of Search: 455/78, 455/63.3, 455/82, 455/550.1, 455/552.1, 455/556.2, 257/212, 257/213
• US Class Current: 455/78
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

Embodiments of the invention may provide for a CMOS antenna switch, which may be referred to as a CMOS SP4T switch. The CMOS antenna switch may operate at a plurality of frequencies, perhaps around 900 MHz and 1.9 GHz according to an embodiment of the invention. The CMOS antenna switch may include both a receiver switch and a transmit switch. The receiver switch may utilize a multi-stack transistor with body substrate tuning to block high power signals from the transmit path as well as to maintain low insertion loss at the receiver path. On the other hand, in the transmit switch, a body substrate tuning technique may be applied to maintain high power delivery to the antenna. Example embodiments of the CMOS antenna switch may provide for 31 dBm P 1 dB at both bands (e.g., 900 MHz and 1.8 GHz). In addition, a 0.9 dB and −1.1 dB insertion loss at 900 MHz and 1.9 GHz, respectively, may be obtained according to example embodiments of the invention.

Claims

1. A CMOS antenna switch, comprising:

a transmit switch in communication with an antenna operative at a plurality of radio frequency (RF) bands;

a receiver switch in communication with the antenna, wherein the receiver switch comprises a plurality of stacked transistors to provide a receive signal path, the plurality of stacked transistors including a first transistor having a body substrate; and

at least one body switch, wherein the at least one body switch is configured to selectively connect the body substrate to either a resistance or ground,

wherein when the transmit switch is enabled, the at least one body switch connects the body substrate of the first transistor to ground, thereby reducing leakage current in the receive signal path,

wherein when the receiver switch is enabled, the at least one body switch connects the body substrate of the first transistor to the resistance, thereby reducing an insertion loss of the receive signal path.

2. The antenna switch of claim 1, wherein the at least one body switch comprises a body switching transistor.

3. The antenna switch of claim 2, wherein the body switching transistor includes a source and a drain, wherein the source is electrically connected to the body substrate of the first transistor and the drain is connected to ground.

4. The antenna switch of claim 1, wherein the plurality of transistors includes a second transistor having a second body substrate, and further comprising:

at least one second body switch, wherein the at least one body switch is configured to selectively connect the second body substrate to either a second resistance or ground,

wherein the first transistor is provided for controlling, at least in part, a first receive signal path of the receiver switch, and wherein the second transistor is provided for controlling, at least in part, a second receive signal path of the receiver switch.

5. The antenna switch of claim 1, wherein:

during a transmit (Tx) mode, the transmit switch is enabled, the receiver switch is disabled, and the at least one body switch is enabled to connect the body substrate of the first transistor to ground; and

during a receive (Rx) mode, the transmit switch is disabled, the receiver switch is enabled, and the at least one body switch is disabled to provide the resistance between the body substrate of the first transistor and ground.

6. The antenna switch of claim 5, wherein during the transmit (Tx) mode, the receiver switch is disabled at least in part by connecting at least one receive signal path of the receiver switch to ground.

7. The antenna switch of claim 1, wherein the first transistor further includes a first source and a first drain, wherein the plurality of stacked transistors includes a second transistor having a second source and a second drain, wherein the first and second transistors are cascaded by electrically connecting the second drain to the first source.

8. The antenna switch of claim 1, wherein the plurality of stacked transistors is a first plurality of transistors, and wherein the transmit switch includes a second plurality of stacked transistors, wherein at least a portion of the second plurality of stacked transistors are cascaded together.

9. The antenna switch of claim 8, wherein the second plurality of transistors comprise body floating transistors.

10. A method for providing a CMOS antenna switch, comprising:

providing an antenna operative at a plurality of radio frequency (RF) bands;

electrically connecting a transmit switch to the antenna;

electrically connecting a receiver switch to the antenna, wherein the receiver switch comprises a plurality of stacked transistors to provide a receive signal path, the plurality of stacked transistors including a first transistor having a body substrate; and

providing at least one body switch, wherein the at least one body switch is configured to selectively connect the body substrate to either a resistance or ground,

wherein when the transmit switch is enabled, the at least one body switch connects the body substrate of the first transistor to ground, thereby reducing leakage current in the receive signal path,

wherein when the receiver switch is enabled, the at least one body switch connects the body substrate of the first transistor to the resistance, thereby reducing an insertion loss of the receive signal path.

11. The method of claim 10, wherein the at least one body switch comprises a body switching transistor.

12. The method of claim 11, wherein the body switching transistor includes a source and a drain, wherein the source is electrically connected to the body substrate of the first transistor and the drain is connected to ground.

13. The method of claim 10, wherein the plurality of transistors includes a second transistor having a second body substrate, and further comprising:

providing at least one second body switch, wherein the at least one body switch is configured to selectively connect the second body substrate to either a second resistance or ground,

wherein the first transistor is provided for controlling, at least in part, a first receive signal path of the receiver switch, and wherein the second transistor is provided for controlling, at least in part, a second receive signal path of the receiver switch.

14. The method of claim 10, wherein:

during a transmit (Tx) mode, the transmit switch is enabled, the receiver switch is disabled, and the at least one body switch is enabled to connect the body substrate of the first transistor to ground; and

during a receive (Rx) mode, the transmit switch is disabled, the receiver switch is enabled, and the at least one body switch is disabled to provide the resistance between the body substrate of the first transistor and ground.

15. The method of claim 14, wherein during the transmit (Tx) mode, the receiver switch is disabled at least in part by connecting at least one receive signal path of the receiver switch to ground.

16. The method of claim 10, wherein the first transistor further includes a first source and a first drain, wherein the plurality of stacked transistors includes a second transistor having a second source and a second drain, wherein the first and second transistors are cascaded by electrically connecting the second drain to the first source.

17. The method of claim 10, wherein the plurality of transistors is a first plurality of stacked transistors, and wherein the transmit switch includes a second plurality of transistors, wherein at least a portion of the second plurality of stacked transistors are cascaded together.

18. The method of claim 17, wherein the second plurality of transistors comprise body floating transistors.