Method for modeling performance of embedded processors having combined cache and memory hierarchy

• US 7,890,314 B2
• Filed: 12/05/2007
• Issued: 02/15/2011
• Est. Priority Date: 12/05/2007
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Cressman, David C.
• Primary Examiner(s): Craig; Dwin M
• Application Number:
  US11/951,219
• Publication Number:
  US 20090150135A1
• Time in Patent Office: 1,168 Days
• Field of Search: 703/20, 711/151
• US Class Current: 703/20
• CPC Class Codes: G06F 2115/10 Processors
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method allocating firmware objects between different types of memory in a product model based on a frequency of access of each firmware object in trace data. The allocated firmware objects and trace data are used to simulate the performance of the product model. Memory access statistics obtained during the simulation may be used to analyze product model performance in the frequency and time domains.

Claims

1. A method comprising:

determining access frequencies of firmware objects;

ranking the firmware objects based on the access frequency of each firmware object; and

allocating the firmware objects between a high-speed on-chip memory and a cache coupled to an external memory based on the ranking of the firmware objects.

2. A method according to claim 1, wherein the high-speed on-chip memory operates at a higher speed than the cache coupled to the external memory.

3. A method according to claim 1, further comprising

defining a threshold for the frequency of accesses, and allocating firmware objects having access frequencies that exceed the threshold value to a first type of memory.

4. A method according to claim 1, further comprising

allocating firmware objects between the high-speed on-chip memory and the cache coupled to the external memory based on a size of each firmware object.

5. A method according to claim 1, wherein the allocation of each firmware object is based on the access frequency of the firmware object and a size of the firmware object.

6. A method according to claim 1, wherein a firmware object is locked into one of the high-speed on-chip memory and the cache coupled to the external memory.

7. A method according to claim 1, further comprising

processing the trace data using the allocated firmware objects.

8. A method according to claim 7, further comprising

analyzing memory access data acquired during the processing of the trace data to analyze average performance.

9. A method according to claim 7, further comprising

generating a timeline object from memory access data acquired during the processing of the trace data to analyze performance in the time domain.

10. A method according to claim 9, wherein the memory access data includes at least one of cache hits, cache misses, or instruction counts.

11. A method according to claim 9, wherein the time domain is defined by time count, instruction count, interrupt, or other periodic event.

12. The method of claim 1, further comprising:

building a product with an processor connected to a quantity of the high-speed on-chip memory sufficient to store the firmware objects allocated to the high-speed on-chip memory and a quantity of the cache sufficient to store the firmware objects allocated to the cache.

13. The method of claim 1, wherein the determining operation is accomplished by analyzing trace data.

14. A method comprising:

analyzing trace data to obtain information regarding firmware objects;

ranking the firmware objects based on the trace data; and

allocating the firmware objects to a high-speed on-chip memory and a cache coupled to an external memory based on ranking.

15. A method according to claim 14, wherein the high-speed on-chip memory operates at a higher speed than the cache coupled to the external memory.

16. A method according to claim 14, wherein ranking includes

sorting the firmware objects based on access frequency.

17. A method according to claim 16, wherein ranking further includes

assigning values to the firmware objects based on heuristics, and

sorting the firmware objects based on the assigned values.

18. A method according to claim 14, wherein ranking includes

sorting the firmware objects based on the size and access frequency of each firmware object.

19. A method according to claim 14, further comprising

simulating performance by processing the trace data using the allocated firmware objects.

20. A method according to claim 19 wherein, during the simulation, memory access data is acquired in at least one of the time domain or the frequency domain.

21. A method according to claim 20, wherein memory data includes at least one of cache hits, cache misses, or instruction counts.

22. A method according to claim 19, further comprising analyzing memory access data to assess system performance.

23. A method according to claim 22, wherein memory access data is analyzed in the time domain.

24. A method according to claim 22, wherein memory access data is analyzed in the frequency domain to assess average performance.

25. The method of claim 14, further comprising:

building a product with an processor connected to a quantity of the high-speed on-chip memory sufficient to store the firmware objects allocated to the high-speed on-chip memory and a quantity of the cache sufficient to store the firmware objects allocated to the cache.

26. One or more computer readable storage media storing computer executable instructions for executing a computer process for allocating firmware objects to memory, the computer process comprising:

analyzing trace data to obtain information regarding firmware objects;

ranking the firmware objects based on the trace data; and

allocating the firmware objects to a high-speed on-chip memory and a cache coupled to an external memory based on ranking.

27. The one or more computer readable storage media of claim 26, wherein the computer process further comprises:

building a product with an processor connected to a quantity of the high-speed on-chip memory sufficient to store the firmware objects allocated to the high-speed on-chip memory and a quantity of the cache sufficient to store the firmware objects allocated to the cache.