Random number generating circuit, semiconductor integrated circuit, IC card and information terminal device

• US 7,890,560 B2
• Filed: 05/16/2008
• Issued: 02/15/2011
• Est. Priority Date: 09/30/2003
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Fujita, Shinobu, Yasuda, Shinichi
• Primary Examiner(s): Do; Chat C
• Application Number:
  US12/122,503
• Publication Number:
  US 20090157780A1
• Time in Patent Office: 1,005 Days
• Field of Search: 708250-256
• US Class Current: 708/250
• CPC Class Codes: G06F 7/58 Random or pseudo-random number generators

Abstract

A random number generating circuit receives as input a first digital random number signal generated at a first generating rate and produces as output a second digital random number signal having a second generating rate that is twice as high as the first generating rate. A semiconductor integrated circuit, an IC card and an information terminal device comprising the random number circuit is provided.

Claims

1. A random number generating circuit, comprising:

an input that receives a first digital random number signal generated at a first generating rate;

a continuous signal processing unit to process the first digital random number signal so that any of its high and low levels do not repeat more than or equal to a predetermined number of times;

a high-rate signal introducing unit to introduce a signal component corresponding to a second generating rate that is twice as high as the first generating rate into the first digital random number signal;

a smoothing unit to control a frequency of occurrence for the high and low levels in a data sequence of the first digital random number signal; and

an output to thereby output the second digital random number signal having a second generating rate, the second digital random number signal generated by outputs from the continuous signal processing unit, the high-rate signal introducing unit, and the smoothing unit,

wherein the high-rate signal introducing unit introduces the signal component corresponding to the second generating rate by detecting a rising and falling edge of the levels in the first digital random number signal generated at the first generating rate by using a clock having a frequency that is twice as high as a frequency of a clock used to generate the first digital random number signal at the first generating rate.

2. The random number generating circuit according to claim 1, wherein the continuous signal processing unit includes:

a counter to count the number of continued repetitions of any of the high and low levels; and

a first combining unit to output a level different from the repeated level when the number of continued repetitions measured by the counter exceeds a predetermined value.

3. The random number generating circuit according to claim 2, wherein the smoothing unit includes:

a shift register to shift the first digital random number signal;

a decoder to decode an output of the counter;

a selector to select a number of shifts in the shift register based on an output of the decoder; and

a second combining unit to combine the first digital random number signal shifted by the shift register and the first digital random number signal not shifted by the shift register.

4. The random number generating circuit according to claim 1, wherein the continuous signal processing unit includes:

a pulse generating unit to output a pulse signal at a fixed interval; and

a first combining unit to combine the first digital random number signal inputted and the pulse signal for output.

5. The random number generating circuit according to claim 1, wherein the smoothing unit includes:

a shift register to shift the first digital random number signal; and

a first combining unit to combine the first digital random number signal shifted by the shift register and the first digital random number signal not shifted by the shift register.

6. The random number generating circuit according to claim 5, wherein the first combining unit outputs an exclusive-OR between the first digital random number signal shifted by the shift register and the first digital random number signal not shifted by the shift register.

7. A semiconductor integrated circuit, comprising:

a random number generating circuit that receives as an input a first digital random number signal generated at a first generating rate,

wherein the random number generating circuit includes;

a continuous signal processing unit to process the first digital random number signal so that any of its high and low levels do not repeat more than or equal to a predetermined number of times;

a high-rate signal introducing unit to introduce a signal component corresponding to a second generating rate that is twice as high as the first generating rate into the first digital random number signal;

a smoothing unit to control a frequency of occurrence for the high and low levels in a data sequence of the first digital random number signal; and

an output to thereby output a second digital random number signal having the second generating rate, the second digital random number signal generated by outputs from the continuous signal processing unit, the high-rate signal introducing unit, and the smoothing unit,

wherein the high-rate signal introducing unit introduces the signal component corresponding to the second generating rate by detecting a rising and falling edge of the levels in the first digital random number signal generated at the first generating rate by using a clock having a frequency that is twice as high as a frequency of a clock used to generate the first digital random number signal at the first generating rate.

8. The semiconductor integrated circuit according to claim 7, wherein the continuous signal processing unit includes:

a counter to count the number of continued repetitions of any of the high and low levels; and

a first combining unit to output a level different from the repeated level when the number of continued repetitions measured by the counter exceeds a predetermined value.

9. An IC card, comprising:

a semiconductor integrated circuit including a random number generating circuit that receives as an input a first digital random number signal generated at a first generating rate,

wherein the random number generating circuit includes;

a continuous signal processing unit to process the first digital random number signal so that any of its high and low levels do not repeat more than or equal to a predetermined number of times;

a high-rate signal introducing unit to introduce a signal component corresponding to a second generating rate that is twice as high as the first generating rate into the first digital random number signal;

a smoothing unit to control a frequency of occurrence for the high and low levels in a data sequence of the first digital random number signal; and

an output to thereby output a second digital random number signal having the second generating rate, the second digital random number signal generated by outputs from the continuous signal processing unit, the high-rate signal introducing unit, and the smoothing unit,

wherein the high-rate signal introducing unit introduces the signal component corresponding to the second generating rate by detecting a rising and falling edge of the levels in the first digital random number signal generated at the first generating rate by using a clock having a frequency that is twice as high as a frequency of a clock used to generate the first digital random number signal at the first generating rate.

10. The IC card according to claim 9, wherein the continuous signal processing unit includes:

a counter to count the number of continued repetitions of any of the high and low levels; and

a first combining unit to output a level different from the repeated level when the number of continued repetitions measured by the counter exceeds a predetermined value.

11. An information terminal device, comprising:

a semiconductor integrated circuit including a random number generating circuit that receives as an input a first digital random number signal generated at a first generating rate,

wherein the random number generating circuit includes;

a continuous signal processing unit to process the first digital random number signal so that any of its high and low levels do not repeat more than or equal to a predetermined number of times;

a high-rate signal introducing unit to introduce a signal component corresponding to a second generating rate that is twice as high as the first generating rate into the first digital random number signal;

a smoothing unit to control a frequency of occurrence for the high and low levels in a data sequence of the first digital random number signal; and

an output to thereby output a second digital random number signal having the second generating rate, the second digital random number signal generated by outputs from the continuous signal processing unit, the high-rate signal introducing unit, and the smoothing unit,

wherein the high-rate signal introducing unit introduces the signal component corresponding to the second generating rate by detecting a rising and falling edge of the levels in the first digital random number signal generated at the first generating rate by using a clock having a frequency that is twice as high as a frequency of a clock used to generate the first digital random number signal at the first generating rate.

12. The information terminal device according to claim 11, wherein the continuous signal processing unit includes:

a counter to count the number of continued repetitions of any of the high and low levels; and

a first combining unit to output a level different from the repeated level when the number of continued repetitions measured by the counter exceeds a predetermined value.