Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture
First Claim
1. A multi-threaded microprocessor for processing instructions in threads, the microprocessor comprising:
- first and second decode pipelines;
first and second execute pipelines;
coupling circuitry operable in a first mode to couple first and second threads from said first and second decode pipelines to said first and second execute pipelines respectively, and said coupling circuitry operable in a second mode to couple different instructions from the first thread to both said first and second execute pipelines for execution, at a same time, of a first instruction in the different instructions by said first execute pipeline and of a second instruction in the different instructions by said second execute pipeline; and
issue circuitry respectively coupled at least to said first and second decode pipelines and to said first and second execute pipelines, wherein said first and second execute pipelines are for executing instructions of threads; and
control circuitry having a storage for thread priorities and enabled thread identifications, the control circuitry for selecting from among a plurality of enabled threads at least a first enabled thread having a first respective priority and a second enabled thread having a second respective priority, wherein the selected enabled thread is selected in response to having a respective priority higher than a priority of another thread in the plurality of enabled threads or than of a thread in one of the first or second execute pipelines, and for launching in the first mode the first selected thread into the first decode pipeline and the second selected thread into the second decode pipeline such that the first selected thread is executed by the first execute pipeline at a same time the second selected thread is executed by the second execute pipeline.
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Abstract
A multi-threaded microprocessor (1105) for processing instructions in threads. The microprocessor (1105) includes first and second decode pipelines (1730.0, 1730.1), first and second execute pipelines (1740, 1750), and coupling circuitry (1916) operable in a first mode to couple first and second threads from the first and second decode pipelines (1730.0, 1730.1) to the first and second execute pipelines (1740, 1750) respectively, and the coupling circuitry (1916) operable in a second mode to couple the first thread to both the first and second execute pipelines (1740, 1750). Various processes of manufacture, articles of manufacture, processes and methods of operation, circuits, devices, and systems are disclosed.
181 Citations
23 Claims
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1. A multi-threaded microprocessor for processing instructions in threads, the microprocessor comprising:
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first and second decode pipelines; first and second execute pipelines; coupling circuitry operable in a first mode to couple first and second threads from said first and second decode pipelines to said first and second execute pipelines respectively, and said coupling circuitry operable in a second mode to couple different instructions from the first thread to both said first and second execute pipelines for execution, at a same time, of a first instruction in the different instructions by said first execute pipeline and of a second instruction in the different instructions by said second execute pipeline; and issue circuitry respectively coupled at least to said first and second decode pipelines and to said first and second execute pipelines, wherein said first and second execute pipelines are for executing instructions of threads; and control circuitry having a storage for thread priorities and enabled thread identifications, the control circuitry for selecting from among a plurality of enabled threads at least a first enabled thread having a first respective priority and a second enabled thread having a second respective priority, wherein the selected enabled thread is selected in response to having a respective priority higher than a priority of another thread in the plurality of enabled threads or than of a thread in one of the first or second execute pipelines, and for launching in the first mode the first selected thread into the first decode pipeline and the second selected thread into the second decode pipeline such that the first selected thread is executed by the first execute pipeline at a same time the second selected thread is executed by the second execute pipeline. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A telecommunications unit comprising:
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a wireless modem; and a multi-threaded microprocessor for processing instructions of a real-time phone call-related thread and a non-real-time thread, said microprocessor coupled to said wireless modem and said microprocessor comprising; a fetch unit; first and second decode pipelines coupled to said fetch unit; first and second execute pipelines; and coupling circuitry having a storage for thread priorities and enabled thread identifications, the coupling circuitry for selecting, from among a plurality of enabled threads, the real-time phone call-related thread having a first respective priority and the non-real-time thread having a second respective priority, wherein the real-time phone call-related thread is selected in response to having a respective priority higher than a priority of another thread in the plurality of enabled threads or than of a thread in one of the first or second execute pipelines, the coupling circuitry further operable in a first mode to couple the real-time phone call-related thread and non-real-time thread from said first and second decode pipelines to said first and second execute pipelines respectively, and said coupling circuitry operable in a second mode to couple a first instruction from the real-time phone call-related thread to said first execute pipeline and a second instruction from the real-time phone call-related thread, different from the first instruction, to said second execute pipelines; and a microphone coupled to said multi-threaded microprocessor.
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Specification