Compressing test responses using a compactor

• US 7,890,827 B2
• Filed: 06/18/2010
• Issued: 02/15/2011
• Est. Priority Date: 02/13/2003
• Status: Active Grant

• Current Assignee: Mentor Graphics Corporation (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Wang, Chen, Mrugalski, Grzegorz, Pogiel, Artur, Tyszer, Jerzy, Rajski, Janusz
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US12/818,941
• Publication Number:
  US 20100257417A1
• Time in Patent Office: 242 Days
• Field of Search: 714/724, 714/726, 714/728, 714/729, 714/731, 714/732, 714/733
• US Class Current: 714/732
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test
• CPC Class Codes: G01R 31/318583 Design for test
• CPC Class Codes: G01R 31/31921 using compression techniques, e.g. patterns sequencer
• CPC Class Codes: G11C 2029/3202 Scan chain
• CPC Class Codes: G11C 29/40 using compression techniques
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.

Claims

1. A method for testing an integrated circuit, comprising:

capturing multiple test values in a scan chain of a circuit-under-test, the test values being associated with a circuit response to a test pattern;

clocking the test values out of the scan chain and into a compactor;

producing sets of two or more output values in the compactor, each set comprising all values produced in the compactor at least partially determined by a respective test value; and

outputting at least one of the sets from the compactor over at least two clock cycles and before all of the test values captured in the scan chain have been clocked into the compactor.

2. The method of claim 1, wherein the act of producing the sets of two or more output values comprises:

producing intermediate values via logic; and

loading the intermediate values into a plurality of memory elements.

3. The method of claim 2, wherein the plurality of memory elements are at least partially coupled by feedback-free logic.

4. The method of claim 1, further comprising locating a source of an error in the scan chain based on the output values.

5. The method of claim 1, further comprising diagnosing faults in the test value using the sets of two or more output values.

6. An integrated circuit comprising a compactor configured to perform the method of claim 1.

7. A computer-readable medium storing a design database that includes design information for a compactor configured to perform the method of claim 1.

8. A computer-readable medium storing computer-executable instructions which when executed by a computer system cause the computer system to perform a method, the method comprising:

modifying a circuit design database to include circuit design information, the circuit design information defining a compactor that is configured to;

capture multiple test values in a scan chain of a circuit-under-test, the test values being associated with a circuit response to a test pattern;

clock the test values out of the scan chain and into the compactor;

produce sets of two or more output values in the compactor each set comprising all values produced in the compactor at least partially determined by a respective test value; and

output at least one of the sets from the compactor over at least two clock cycles and before all of the test values captured in the scan chain have been clocked into the compactor.

9. The computer-readable medium of claim 8, wherein the compactor defined by the circuit design information is further configured to perform the act of producing the sets of two or more output values by:

producing intermediate values via logic; and

loading the intermediate values into a plurality of memory elements.

10. The computer-readable medium of claim 9, wherein the plurality of memory elements are at least partially coupled by feedback-free logic.

11. A system, comprising:

means for capturing multiple test values in a scan chain of a circuit-under-test, the test values being associated with a circuit response to a test pattern;

means for clocking the test values out of the scan chain and into a compactor;

means for producing sets of two or more output values in the compactor, each set comprising all values produced in the compactor at least partially determined by a respective test value; and

means for outputting at least one of the sets from the compactor over at least two clock cycles and before all of the test values captured in the scan chain have been clocked into the compactor.

12. The system of claim 11, wherein the means for producing the sets of two or more output values comprises:

means for producing intermediate values via logic; and

means for loading the intermediate values into a plurality of memory elements.

13. The system of claim 12, wherein the plurality of memory elements are at least partially coupled by feedback-free logic.

14. The system of claim 11, further comprising means for locating a source of an error in the scan chain based on the output values.

15. The system of claim 11, further comprising means for diagnosing faults in the test value using the sets of two or more output values.