Method and apparatus improving gate oxide reliability by controlling accumulated charge

• US 7,890,891 B2
• Filed: 09/14/2006
• Issued: 02/15/2011
• Est. Priority Date: 07/11/2005
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Kim, Tae Youn, Stuber, Michael A., Imthurn, George P., Dribinsky, Alexander, Kelly, Dylan J., Brindle, Christopher N., Welstand, Robert B., Burgener, Mark L., Kemerling, Clint L.
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): Tat; Binh C
• Application Number:
  US11/520,912
• Publication Number:
  US 20070069291A1
• Time in Patent Office: 1,615 Days
• Field of Search: 716/1, 716/2, 716/18, 716/8
• US Class Current: 716/102
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/78651 Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78657 SOS transistors
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit

Abstract

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

Claims

1. A circuit, comprising:

a) a semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) having improved gate oxide reliability, wherein the SOI MOSFET is implemented so that it is adapted to have a specified value of a reliability property of a gate oxide of the SOI MOSFET, wherein the implementation of the MOSFET is responsive to a first value of a reliability property of the gate oxide having an uncontrolled accumulated charge proximate the gate oxide and wherein the implementation of the MOSFET is further responsive to a second value of the reliability property of the gate oxide having a controlled accumulated charge proximate the gate oxide; and

b) a means for accumulated charge control (ACC) operatively coupled to the SOI MOSFET;

wherein the reliability property of the gate oxide comprises a maximum electric field present in the gate oxide, and wherein the specified value of the reliability property comprises an electric field value E_tb corresponding to a selected average time-to-breakdown for the gate oxide, and wherein the SOI MOSFET is adapted to have the specified value of the reliability property of the gate oxide by applying a second limiting gate bias voltage V_g2 to a gate of the SOI MOSFET, wherein the second limiting gate bias voltage V_g2 has an absolute value that is greater than the absolute value of a first limiting gate bias voltage V_g1 applied to the gate of the SOI MOSFET, and wherein the first limiting gate bias voltage V_g1 corresponds to the SOI MOSFET having the specified value of the reliability property without the means for ACC operatively coupled to the SOI MOSFET.

2. The circuit of claim 1, wherein the first value of the reliability property is determined by simulating operation of the SOI MOSFET to determine a first maximum electric field E_ox1 in the gate oxide with the uncontrolled accumulated charge proximate the gate oxide, and wherein the second value of the reliability property is determined by simulating operation of the SOI MOSFET to determine a second maximum electric field E_ox2 in the gate oxide with the controlled accumulated charge proximate the gate.

3. The circuit of claim 1, wherein the SOI MOSFET is adapted to have the specified value of the reliability property of the gate oxide by implementing a second thickness T_ox2 of the gate oxide, wherein the second thickness T_ox2 is less than a first thickness T_ox1 of the gate oxide, wherein the first thickness T_ox1 corresponds to the SOI MOSFET having the specified value of the reliability property without the means for ACC operatively coupled to the SOI MOSFET.

4. The circuit of claim 3, wherein the SOI MOSFET is adapted to enable a specified performance using the second thickness T_ox2, and a second body width W2 of the SOI MOSFET, wherein the second body width W2 is less than a first body width W1 of the SOI MOSFET, and wherein the first body width W1 corresponds to the SOI MOSFET adapted to enable the specified performance using the first thickness T_ox1.

5. The circuit of claim 1, wherein the means for ACC comprises an Accumulated Charge Sink (ACS) having a resistance greater than 10⁶ ohm, and wherein the ACS is operatively coupled to a body region of the SOI MOSFET to receive the accumulated charge.

6. The circuit of claim 1, wherein the means for ACC comprises an Accumulated Charge Sink (ACS) having a resistance not greater than 10⁶ ohm, and wherein the ACS is operatively coupled to a body region of the SOI MOSFET to receive the accumulated charge.

7. The circuit of claim 1, wherein the means for ACC comprises a control circuit operatively coupled to a gate of the SOI MOSFET, wherein the control circuit applies a voltage pulse to the gate that switches the SOI MOSFET from an accumulated charge regime to a non-accumulated charge regime for a selected interval.

8. The circuit of claim 1, wherein the means for ACC comprises a resistor electrically connected to a gate of the SOI MOSFET sufficient to prevent attenuation of an induced RF voltage on the gate, and wherein an RF signal voltage having a selected frequency is applied to a drain of the SOI MOSFET thereby generating the induced RF voltage, and wherein the induced RF voltage transitions the SOI MOSFET from an accumulated charge regime to a non-accumulated charge regime for part of a cycle of the RF signal voltage.

9. The circuit of claim 1, wherein the SOI MOSFET comprises an N MOSFET.

10. The circuit of claim 1, wherein the SOI MOSFET comprises a P MOSFET.

11. The circuit of claim 1, wherein the SOI MOSFET comprises an SOI MOSFET selected from the following types:

a silicon-on-sapphire (SOS) SOI MOSFET, a silicon-germanium (SiGe) SOI MOSFET, a Separation by Implantation of Oxygen (SIMOX) SOI MOSFET, and a silicon bonded to insulator SOI MOSFET.

12. The circuit of claim 1, wherein the circuit comprises a circuit selected from the following types:

an RF switching circuit, an RF mixer, a power amplifier, a level shifting circuit, a negative voltage generator, an oscillator, and a DC-DC converter.

13. A method for improving gate oxide reliability of a semiconductor-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET), comprising the steps of:

a) determining a first value of a reliability property for a gate oxide of an SOI MOSFET when the SOI MOSFET has an uncontrolled accumulated charge proximate to the gate oxide;

b) determining a second value of the reliability property for the gate oxide of the SOI MOSFET when the SOI MOSFET has a controlled accumulated charge proximate the gate oxide;

c) responsive to the determining steps a) and b), implementing the SOI MOSFET so that it is adapted to have a specified reliability property value for the gate oxide; and

d) controlling the accumulated charge proximate the gate oxide;

wherein the reliability property for the gate oxide comprises a maximum electric field present in the gate oxide, and wherein the specified reliability property value comprises an electric field value E_tb corresponding to a selected average time-to-breakdown for the gate oxide, and wherein the SOI MOSFET is adapted in step c) to have the specified reliability property value for the gate oxide by applying a second limiting gate bias voltage V_g2 to a gate of the SOI MOSFET, wherein the second limiting gate bias voltage V_g2 has an absolute value that is greater than the absolute value of a first limiting gate bias voltage V_g1 applied to the gate of the SOI MOSFET, and wherein the first limiting gate bias voltage V_g1 corresponds to the SOI MOSFET having the specified reliability property value without controlling the accumulated charge proximate the gate oxide.

14. The method of claim 13, wherein the STEP a) of determining a first value of the reliability property comprises simulating operation of the SOI MOSFET to determine a first electric field E_ox1 in the gate oxide with the uncontrolled accumulated charge proximate the gate oxide, and wherein the STEP b) of determining a second value of the reliability property comprises simulating operation of the SOI MOSFET to determine a second electric field E_ox2 in the gate oxide with the controlled accumulated charge proximate the gate.

15. The method of claim 13, wherein the SOI MOSFET is adapted in step c) to have the specified reliability property value for the gate oxide by implementing a second thickness T_ox2 of the gate oxide, wherein the second thickness T_ox2 is less than a first thickness T_ox1 of the gate oxide, wherein the first thickness T_ox1 corresponds to the SOI MOSFET having the specified reliability property value without controlling the accumulated charge proximate the gate oxide.

16. The method of claim 15, wherein the SOI MOSFET is adapted to enable a specified performance using the second thickness T_ox2 and a second body width W2 of the SOI MOSFET, wherein the second body width W2 is less than a first body width W1 of the SOI MOSFET, and wherein the first body width W1 corresponds to the SOI MOSFET adapted to enable the specified performance using the first thickness T_ox1.

17. The method of claim 13, wherein the step d) of controlling the accumulated charge comprises operatively coupling an Accumulated Charge Sink (ACS), having a resistance greater than 10⁶ ohm, to a body region of the SOI MOSFET to receive the accumulated charge.

18. The method of claim 13, wherein the step d) of controlling the accumulated charge comprises operatively coupling an Accumulated Charge Sink (ACS), having a resistance not greater than 10⁶ ohm, to a body region of the SOI MOSFET to receive the accumulated charge.

19. The method of claim 13, wherein the step d) of controlling the accumulated charge comprises operatively coupling a control circuit to a gate of the SOI MOSFET, wherein the control circuit applies a voltage pulse to the gate that switches the SOI MOSFET from an accumulated charge regime to a non-accumulated charge regime for a selected interval.

20. The method of claim 13, wherein the step d) of controlling the accumulated charge comprises electrically coupling a resistor to a gate of the SOI MOSFET sufficient to prevent attenuation of an induced RF voltage on the gate, and wherein an RF signal voltage having a selected frequency is applied to a drain of the SOI MOSFET thereby generating the induced RF voltage, and wherein the induced RF voltage transitions the SOI MOSFET from an accumulated charge regime to a non-accumulated charge regime for part of a cycle of the RF signal voltage.

21. The method of claim 13, wherein the SOI MOSFET comprises an N MOSFET.

22. The method of claim 13, wherein the SOI MOSFET comprises a P MOSFET.

23. The method of claim 13, wherein the SOI MOSFET comprises an SOI MOSFET selected from the following types:

a silicon-on-sapphire (SOS) SOI MOSFET, a silicon-germanium (SiGe) SOI MOSFET, a Separation by Implantation of Oxygen (SIMOX) SOI MOSFET, and a silicon bonded to insulator SOI MOSFET.

24. The method of claim 13, wherein the SOI MOSFET is implemented in a circuit selected from the following types:

an RF switching circuit, an RF mixer, a power amplifier, a level shifting circuit, a negative voltage generator, an oscillator, and a DC-DC converter.

25. A system for improving gate oxide reliability of a semiconductor-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET), comprising:

a) means for determining a first value of a reliability property for a gate oxide of an SOI MOSFET when the SOI MOSFET has an uncontrolled accumulated charge proximate the gate oxide;

b) means for determining a second value of the reliability property for the gate oxide of the SOI MOSFET when the SOI MOSFET has a controlled accumulated charge proximate the gate oxide;

c) means for implementing the SOI MOSFET in a circuit, wherein the SOI MOSFET is implemented so that it is adapted to have a specified value of the reliability property of the gate oxide, wherein the SOI MOSFET is implemented responsive to the determining means (a) and (b); and

d) means for controlling the accumulated charge proximate the gate oxide;

wherein the reliability property for the gate oxide comprises a maximum electric field present in the gate oxide, and wherein the specified value of the reliability property comprises an electric field value E_tb corresponding to a selected average time-to-breakdown for the gate oxide, and wherein the SOI MOSFET is adapted to have the specified value of the reliability property of the gate oxide by applying a second limiting gate bias voltage V_g2 to a gate of the SOI MOSFET, wherein the second limiting gate bias voltage V_g2 has an absolute value that is greater than the absolute value of a first limiting gate bias voltage V_g1 applied to the gate of the SOI MOSFET, and wherein the first limiting gate bias voltage V_g1 corresponds to the SOI MOSFET having the specified value of the reliability property without controlling the accumulated charge proximate the gate oxide.

26. The system of claim 25, wherein the first value of the reliability property is determined by simulating operation of the SOI MOSFET to determine a first electric field E_ox1 in the gate oxide with the uncontrolled accumulated charge proximate the gate oxide, and wherein the second value of the reliability property is determined by simulating operation of the SOI MOSFET to determine a second electric field E_ox2 in the gate oxide with the controlled accumulated charge proximate the gate.

27. The system of claim 25, wherein the SOI MOSFET is adapted to have the specified value of the reliability property of the gate oxide by implementing a second thickness T_ox2 of the gate oxide, wherein the second thickness T_ox2 is less than a first thickness T_ox1 of the gate oxide, wherein the first thickness T_ox1 corresponds to the SOI MOSFET having the specified value of the reliability property without controlling the accumulated charge proximate the gate oxide.

28. The system of claim 27, wherein the SOI MOSFET is adapted to enable a specified performance using the second thickness T_ox2 and a second body width W2 of the SOI MOSFET, wherein the second body width W2 is less than a first body width W1 of the SOI MOSFET, and wherein the first body width W1 corresponds to the SOI MOSFET adapted to enable the specified performance using the first thickness T_ox1.

29. The system of claim 25, wherein the means for controlling the accumulated charge comprises an Accumulated Charge Sink (ACS) having a resistance greater than 10⁶ ohm, and wherein the ACS is operatively coupled to a body region of the SOI MOSFET to receive the accumulated charge.

30. The system of claim 25, wherein the means for controlling the accumulated charge comprises an Accumulated Charge Sink (ACS) having a resistance not greater than 10⁶ ohm, and wherein the ACS is operatively coupled to a body region of the SOI MOSFET to receive the accumulated charge.

31. The system of claim 25, wherein the means for controlling the accumulated charge comprises a control circuit operatively coupled to a gate of the SOI MOSFET, wherein the control circuit applies a voltage pulse to the gate that switches the SOI MOSFET from an accumulated charge regime to a non-accumulated charge regime for a selected interval.

32. The system of claim 25, wherein the means for controlling the accumulated charge comprises a resistor electrically connected to a gate of the SOI MOSFET sufficient to prevent attenuation of an induced RF voltage on the gate, and wherein an RF signal voltage having a selected frequency is applied to a drain of the SOI MOSFET thereby generating the induced RF voltage, and wherein the induced RF voltage transitions the SOI MOSFET from an accumulated charge regime to a non-accumulated charge regime for part of a cycle of the RF signal voltage.

33. The system of claim 25, wherein the SOI MOSFET comprises an N MOSFET.

34. The system of claim 25, wherein the SOI MOSFET comprises a P MOSFET.

35. The system of claim 25, wherein the SOI MOSFET comprises an SOI MOSFET selected from the following types:

a silicon-on-sapphire (SOS) SOI MOSFET, a silicon-germanium (SiGe) SOI MOSFET, a Separation by Implantation of Oxygen (SIMOX) SOT MOSFET, and a silicon bonded to insulator SOI MOSFET.

36. The system of claim 25, wherein the circuit comprises a circuit selected from the following types:

an RF switching circuit, an RF mixer, a power amplifier, a level shifting circuit, a negative voltage generator, an oscillator, and a DC-DC converter.