Statistical delay and noise calculation considering cell and interconnect variations

• US 7,890,915 B2
• Filed: 03/17/2006
• Issued: 02/15/2011
• Est. Priority Date: 03/18/2005
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Jiayong Le, Mustafa Celik
• Inventors: Celik, Mustafa, Le, Jiayong
• Primary Examiner(s): Doan; Nghia M
• Application Number:
  US11/918,760
• Publication Number:
  US 20090288050A1
• Time in Patent Office: 1,796 Days
• Field of Search: 716 1- 3, 716 5- 6, 716/18, 703/2, 703 13- 14
• US Class Current: 716/113
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

The electrical circuit timing method provides accurate nominal delay together with the delay sensitivities with respect to different circuit elements {e.g., cells, interconnects, etc.) and variational parameters (e.g., process variations; environmental variations). All the sensitivity computations are based on closed-form formulas; as a consequence, the method provides rapidly and at low cost high accuracy and high numerical stability.

Claims

1. A method for determining delay in static timing analysis of an integrated circuit of interest, said integrated circuit comprised of a plurality of logic cells, where said delay as determined is expressed as a parametric function, said parametric function containing statistical manufacturing process variations introduced by the process of manufacturing said logic cells of said integrated circuit, said method comprising the steps of:

a) calculating, said calculating performed by means of a computational device said computational device including a CPU, a driving circuit for a first logic cell of said integrated circuit of interest, said driving circuit containing in parametric form manufacturing process variations of said integrated circuit, said calculating said driving circuit including the sub-steps of;

1. calculating a compact interconnect load for said first logic cell, said compact interconnect load containing in parametric form manufacturing process variations, wherein said calculating said compact interconnect load for said first logic cell further includes

matching the statistical moment of the non-compacted interconnect load of said first logic cell where said statistical moment contains parametric form of manufacturing process variations,

and wherein calculating said statistical moment includes the substeps of;

evuluating, said non-compacted interconnect load of said first logic cell and

calculating the corresponding moment sensitivity from the parametric sensitivity of said non-compacted interconnect load of said first logic cell by the substeps of;

calculating, by applying adjoint circuit techniques said moment sensitivities, and

calculating said moment sensitivities through multiple evaluations of different adjoint circuits under variant voltage and current sources;

2. calculating, using said compact interconnect load of sub-step 1, an effective capacitance with respect to said first logic cell, said effective capacitance representing a distribution of load, and where said calculation of said effective capacitance is derived by matching the current that goes through said statistical compact load in sub-step 1 with the current that goes through an effective capacitance, as described in the equations

2. A non-transitory computer readable medium containing an executable program having instructions to direct a central processing unit to determine the delay in static timing analysis of a plurality of interconnected logic cells comprising an integrated circuit of interest, where said program comprises instructions to direct the computer to perform the steps of:

a) calculating, said calculating perfomed by means of a computational device said computational device including a CPU, a driving circuit for a first logic cell of said integrated circuit of interest, said driving circuit containing in parametric form manufacturing process variations of said integrated circuit, said calculating said driving circuit including the sub-steps of ;

1. calculating a compact interconnect load for said first logic cell, said compact interconnect load containing in parametric form manufacturing process variations, wherein said calculating said compact interconnect load for said first logic cell further includes

matching the statistical moment of the non-compacted interconnect load of said first logic cell where said statistical moment contains parametric form of manufacturing process variations,

and wherein calculating said statistical moment includes the substeps of;

evaluating, said non-compacted interconnect load of said first logic cell and

calculating the corresponding moment sensitivity from the parametric sensitivity of said non-compacted interconnect load of said first logic cell by the substeps of;

calculating, by applying adjoint circuit techniques said moment sensitivities, and

calculating said moment sensitivities through multiple evaluations of different adjoint circuits under variant voltage and current sources;

2. calculating, using said compact interconnect load of sub-step 1, an effective capacitance with respect to said first logic cell, said effective capacitance representing a distribution of load, and where said calculation of said effective capacitance is derived by matching the current that goes through said statistical compact load in sub-step 1 with the current that goes through an effective capacitance, as described in the equations

3. A computer output product produced by the process of analyzing timing of an integrated circuit of interest, said integrated circuit comprised of a plurality of logic cells, the process comprising the steps of:

a) calculating, said calculating performed by means of a computational device said computational device including a CPU, a driving circuit for a first logic cell of said integrated circuit of interest, said driving circuit containing in parametric form manufacturing process variations of said integrated circuit, said calculating said driving circuit including the sub-steps of;

1. calculating a compact interconnect load for said first logic cell, said compact interconnect load containing in parametric form manufacturing process variations, wherein said calculating said compact interconnect load, for said first logic cell further includes

matching the statistical moment of the non-compacted interconnect load of said first logic cell where said statistical moment contains parametric form of manufacturing process variations,

and wherein calculating said statistical moment includes the substeps of;

evaluating, said non-compacted interconnect load of said first logic cell and

calculating the corresponding moment sensitivity from the parametric sensitivity of said non-compacted interconnect load of said first logic cell by the substeps of;

calculating, by applying adjoint circuit techniques said moment sensitivities, and

calculating said moment sensitivities through multiple evaluations of different adjoint circuits under variant voltage and current sources;

2. calculating, using said compact interconnect load of sub-step 1, an effective capacitance with respect to said first logic cell, said effective capacitance representing a distribution of load, and where said calculation of said effective capacitance is derived by matching the current that goes through said statistical compact load in sub-step 1 with the current that goes through an effective capacitance, as described in the equations