Debugging using a virtual file system interface

• US 7,890,916 B1
• Filed: 03/25/2008
• Issued: 02/15/2011
• Est. Priority Date: 03/25/2008
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: So, Hayden Kwok-Hay, Hartke, Paul M., Lysaght, Patrick, Blodget, Brandon J., Donlin, Adam P.
• Primary Examiner(s): Dinh; Paul
• Assistant Examiner(s): Nguyen; Nha T
• Application Number:
  US12/055,163
• Time in Patent Office: 1,057 Days
• Field of Search: 716/4, 716/16, 716/17, 716/106, 716/108, 716/116, 716/117
• US Class Current: 716/116
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

Various approaches for controlling a circuit implemented on an integrated circuit device having programmable logic. According to one approach a hierarchy of directories and files are maintained in a virtual file system that is registered with an operating system. The directories and files are associated with resources of the programmable logic. Each file represents a respective data set of configuration data for an associated one of the resources, and at least one of the files is a clock control file that is associated with a clock control circuit on the integrated circuit. A first value is stored in the clock control circuit of the programmable logic in response to invocation of an operating system file access command that references the clock control file and specifies the first value. Advancement of a clock signal on the programmable logic is controlled in response to the first value stored in the clock control circuit.

Claims

1. A processor-implemented method for controlling a circuit implemented in an integrated circuit having programmable logic, the method comprising:

maintaining a hierarchy of directories and files in a virtual file system that is registered with an operating system, wherein the directories and files are associated with resources of the programmable logic, wherein the programmable logic includes a plurality of configurable clock management circuits of the programmable logic, each clock management circuit configurable to de-skew an input clock signal and provide an output clock signal from the de-skewed input clock signal, and configurable to change the frequency of an input clock signal and provide the output clock signal at the change frequency, and each file represents a respective data set of configuration data for an associated one of the resources, a plurality of clock control files respectively associated with clock control circuits of the programmable logic and each clock control circuit coupled to a respective one of the configurable clock management circuits;

wherein the operating system executes on a processor, and the processor is coupled to the resources of the programmable logic;

storing a first value in each of the associated clock control circuits in response to a plurality of corresponding invocations of one or more operating system file access commands, each invocation referencing one of the clock control files and specifying the first value; and

controlling advancement of each output clock signal from each clock management circuit of the programmable logic in response to the first value stored in the clock control circuits.

2. The method of claim 1, wherein the controlling includes stopping the clock in response to the first value being equal to a first logic level.

3. The method of claim 2, wherein the controlling includes starting the clock in response to the first value being equal to a second logic level.

4. The method of claim 1, wherein the controlling includes advancing the clock signal for a number of cycles specified by the first value.

5. The method of claim 1, wherein the files include a respective file for each clock management circuit, the method further comprising:

storing a second value in the one of the clock management circuits of the programmable logic in response to invocation of an operating system file access command that specifies the second value and that references the file associated with the one of the plurality of clock management circuits; and

controlling one of a de-skewing function and frequency change function of the one of the clock management circuits in response to the second value stored in the one of the clock management circuits.

6. The method of claim 1, further comprising:

in response to a plurality of corresponding invocations of one or more operating system file access commands, each invocation referencing one of the clock control files and specifying the first value, for each clock control circuit associated with a referenced clock control file, determining from the first value, a respective cycle count for the output clock signal of the clock management circuit that is coupled to the clock control circuit, wherein two or more of the clock management circuits output respective clock signals having different signal characteristics;

storing the respective cycle counts in the clock control circuits; and

advancing each output clock signal by a number of cycles specified by the respective cycle count.

7. The method of claim 1, further comprising:

in response to a file system file access command, copying a timing data file to the hierarchy;

generating, in response to the copying, epoch data files, wherein each epoch data file indicates a respective number of clock cycles by which a respective one of the clock management circuits is to advance the output clock signal in order to reach a next state;

in response to a file system file access command that references the epoch data file, copying the epoch data file to a clock control directory and updating the configuration of the clock control associated with the circuit clock control directory in response to the copying of the epoch data file.

8. The method of claim 1, further comprising:

storing in a meta-file, physical resource information in association with a plurality of state elements of a design implemented by the circuit;

copying the meta-file to the hierarchy in response to a file access command, and in response to the copying, creating one or more files in the hierarchy corresponding to the physical resources of the programmable logic identified by the physical resource information;

reading back state data from the physical resources of the programmable logic identified by the physical resource information in response to a file access command that reads from the one or more files.

9. The method of claim 1, further comprising:

creating a first file in the hierarchy corresponding to a first register in a design implemented by the circuit; and

storing a second value in the first register on the programmable logic in response to invocation of an operating system file access command that references the first file and specifies the second value.

10. An apparatus for controlling a circuit implemented in an integrated circuit device having programmable logic, the apparatus comprising:

a processor coupled to the resources of the programmable logic, wherein the programmable logic includes a plurality of configurable clock management circuits of the programmable logic, each clock management circuit configurable to de-skew an input clock signal and provide an output clock signal from the de-skewed input clock signal, and configurable to change the frequency of an input clock signal and provide the output clock signal at the change frequency;

a memory arrangement coupled to the processor and configured with program code that when executed by the processor causes the processor to perform operations including;

maintaining a hierarchy of directories and files in a virtual file system that is registered with an operating system, wherein the directories and files are associated with resources of the integrated circuit device and each file represents a respective data set of configuration data for an associated one of the resources, a plurality of clock control files respectively associated with clock control circuits of the programmable logic and each clock control circuit coupled to a respective one of the configurable clock management circuits;

wherein the operating system executes on the processor;

storing a first value in each of the associated clock control circuits in response to a plurality of corresponding invocations of one or more operating system file access commands, each invocation referencing one of the clock control files and specifying the first value; and

controlling advancement of each output clock signal from each clock management circuit of the programmable logic in response to the first value stored in the clock control circuits.

11. An article of manufacture, comprising:

a non-transitory processor-readable storage medium configured with instructions for controlling a circuit implemented in an integrated circuit device having programmable logic, wherein the programmable logic includes a plurality of configurable clock management circuits of the programmable logic, each clock management circuit configurable to de-skew an input clock signal and provide an output clock signal from the de-skewed input clock signal, and configurable to change the frequency of an input clock signal and provide the output clock signal at the changed frequency, the instructions when executed by a processor coupled to the programmable logic, causing the processor to perform the steps including,

maintaining a hierarchy of directories and files in a virtual file system that is registered with an operating system, wherein the directories and files are associated with resources of the programmable logic and each file represents a respective data set of configuration data for an associated one of the resources, a plurality of clock control files respectively associated with clock control circuits of the programmable logic and each clock control circuit coupled to a respective one of the configurable clock management circuits;

wherein the operating system executes on the processor;

storing a first value in each of the associated clock control circuits in response to a plurality of corresponding invocations of one or more operating system file access commands, each invocation referencing one of the clock control files and specifying the first value; and

controlling advancement of each output clock signal from each clock management circuit of the programmable logic in response to the first value stored in the clock control circuits.

12. The article of manufacture of claim 11, wherein the controlling includes stopping the clock in response to the first value being equal to a first logic level.

13. The article of manufacture of claim 12, wherein the controlling includes stopping the clock in response to the first value being equal to a second logic level.

14. The article of manufacture of claim 11, wherein the controlling includes advancing the clock signal for a number of cycles specified by the first value.

15. The article of manufacture of claim 11, wherein the files include a respective file for each clock management circuit, the steps further comprising:

storing a second value in the one of the clock management circuits on the integrated circuit device in response to invocation of an operating system file access command that specifies the second value and that references the file associated with the one of the plurality of clock management circuits; and

controlling one of a de-skewing function and frequency change function of the one of the clock management circuits in response to the second value stored in the one of the clock management circuits.

16. The article of manufacture of claim 11, the steps further comprising:

in response to a plurality of corresponding invocations of one or more operating system file access commands, each invocation referencing one of the clock control files and specifying the first value, for each clock control circuit associated with a referenced clock control file, determining from the first value, a respective cycle count for the output clock signal of the clock management circuit that is coupled to the clock control circuit, wherein two or more of the clock management circuits output respective clock signals having different signal characteristics;

storing the respective cycle counts in the clock control circuits; and

advancing each output clock signal by a number of cycles specified by the respective cycle count.

17. The article of manufacture of claim 11, the steps further comprising:

in response to a file system file access command, copying a timing data file to the hierarchy;

generating, in response to the copying, epoch data files, wherein each epoch data file indicates a respective number of clock cycles by which a respective one of the clock management circuits is to advance the output clock signal in order to reach a next state;

in response to a file system file access command that references the epoch data file, copying the epoch data file to a clock control directory and updating the configuration of the clock control associated with the circuit clock control directory in response to the copying of the epoch data file.

18. The article of manufacture of claim 11, the steps further comprising:

storing in a meta-file, physical resource information in association with a plurality of state elements of a design implemented by the circuit;

copying the meta-file to the hierarchy in response to a file access command, and in response to the copying, creating one or more files in the hierarchy corresponding to the physical resources of the programmable logic identified by the physical resource information;

reading back state data from the physical resources of the programmable logic identified by the physical resource information in response to a file access command that reads from the one or more files.