Isolation trenches for memory devices

• US 7,892,943 B2
• Filed: 12/21/2007
• Issued: 02/22/2011
• Est. Priority Date: 06/28/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Violette, Michael
• Primary Examiner(s): Hu; Shouxiang
• Assistant Examiner(s): Gebremariam; Samuel A
• Application Number:
  US11/962,967
• Publication Number:
  US 20080128781A1
• Time in Patent Office: 1,159 Days
• Field of Search: 438/201, 438/435, 438/257, 438/258, 438/259, 438/260, 438/261, 438/262, 438/263, 438/264, 438/265, 438/266, 438/267, 438/314, 438/315, 438/316, 438/317, 438/318, 438/319, 438/320, 257/E21.68
• US Class Current: 438/435
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate

Abstract

A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.

Claims

1. A method of forming a portion of a memory device, comprising:

forming a dielectric liner overlying and in direct contact with a portion of a trench that extends into a substrate below an upper surface of the substrate;

forming a first dielectric plug in the portion of a trench that extends into the substrate below the upper surface of the substrate so that an upper surface of the first dielectric plug is recessed below the upper surface of the substrate, the first dielectric plug comprising a layer of a first dielectric material overlying and in direct contact with the dielectric liner and a layer of a second dielectric material formed on the layer of the first dielectric material so that the upper surface of the first dielectric plug comprises an upper surface of the layer of the second dielectric material and a portion of the layer of the first dielectric material coplanar with the upper surface of the layer of the second dielectric material; and

forming a second dielectric plug of a third dielectric material on the upper surface of the first dielectric plug so that the second dielectric plug extends from the upper surface of the first dielectric plug through another portion of the trench that extends above the upper surface of the substrate and that passes through a layer of a fourth dielectric material overlying the upper surface of the substrate and a conductive layer overlying the layer of fourth dielectric material, wherein the second dielectric plug contacts a portion of the layer of fourth dielectric material and a portion of the conductive layer.

2. The method of claim 1, wherein forming the second dielectric plug comprises forming a portion of the second dielectric plug on the dielectric liner.

3. The method of claim 1, wherein the second dielectric plug is a high-density-plasma oxide.

4. The method of claim 1, wherein forming the first dielectric plug further comprises curing the layer of second dielectric material.

5. The method of claim 4, wherein curing the layer of second dielectric material comprises an oxidation process.

6. The method of claim 1 further comprises, after forming the second dielectric plug:

forming a layer of fifth dielectric material overlying the conductive layer; and

forming another conductive layer overlying the layer of fifth dielectric material.

7. A method of forming a portion of a memory device, comprising:

forming a first dielectric plug in a portion of a trench that extends into a substrate below an upper surface of the substrate so that an upper surface of the first dielectric plug is recessed below the upper surface of the substrate, the first dielectric plug comprising a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material; and

forming a second dielectric plug of a third dielectric material on the upper surface of the first dielectric plug so that the second dielectric plug extends from the upper surface of the first dielectric plug through another portion of the trench that extends above the upper surface of the substrate and that passes through a layer of a fourth dielectric material overlying the upper surface of the substrate and a first conductive layer overlying the layer of fourth dielectric material, wherein the second dielectric plug contacts a portion of the layer of fourth dielectric material and a portion of the conductive layer; and

after forming the second dielectric plug;

forming a layer of fifth dielectric material overlying the conductive layer so that an upper surface of the fifth dielectric material is located at a depth below an upper surface of the second dielectric plug; and

forming a second conductive layer overlying the layer of fifth dielectric material.

8. A method of forming a portion of a memory device, comprising:

lining a first portion of a trench that extends into a substrate below an upper surface of the substrate with a first dielectric layer by forming the first dielectric layer on the substrate;

forming a second dielectric layer in the first portion of the trench on the first dielectric layer and in a second portion of the trench that extends above the upper surface of the substrate and that passes through a tunnel dielectric layer overlying the upper surface of the substrate and a floating gate layer overlying the tunnel dielectric layer;

forming a fourth dielectric layer on the second dielectric layer so that the fourth dielectric layer fills a portion of the first portion trench and so that an upper surface of the fourth dielectric layer is located below the upper surface of the substrate;

removing a portion of the second dielectric layer to a level of the upper surface of the fourth dielectric layer to expose a portion of the first dielectric layer located between the upper surface of the fourth dielectric layer and the upper surface of the substrate; and

forming a fifth dielectric layer on the upper surface of the fourth dielectric layer and on the exposed portion of the first dielectric layer so as to fill a remaining portion of the first portion of the trench and to fill the second portion of the trench so that a portion of the fifth dielectric layer filling the second portion of the trench contacts a portion of the tunnel dielectric layer overlying the upper surface of the substrate and a portion of the floating gate layer overlying the tunnel dielectric layer;

after forming the fifth dielectric layer;

forming an intergate dielectric layer overlying the floating gate layer so that an upper surface of the intergate dielectric layer is located at a depth below an upper surface of the fifth dielectric layer; and

forming a control gate overlying the intergate dielectric layer.

9. A method of forming a portion of a memory device, comprising:

lining a first portion of a trench that extends into a substrate below an upper surface of the substrate with a first dielectric layer by forming the first dielectric layer overlying and in direct contact with the substrate;

forming a second dielectric layer in the first portion of the trench overlying and in direct contact with the first dielectric layer and in a second portion of the trench that extends above the upper surface of the substrate and that passes through a third dielectric layer overlying the upper surface of the substrate and a conductive layer overlying the third dielectric layer;

forming a fourth dielectric layer on the second dielectric layer so that the fourth dielectric layer fills a portion of the first portion trench and so that an upper surface of the fourth dielectric layer is located below the upper surface of the substrate;

removing a portion of the second dielectric layer to a level of the upper surface of the fourth dielectric layer to expose a portion of the first dielectric layer located between the upper surface of the fourth dielectric layer and the upper surface of the substrate, and such that a portion of the second dielectric layer is coplanar with the upper surface of the fourth dielectric layer; and

forming a fifth dielectric layer on the upper surface of the fourth dielectric layer and on the exposed portion of the first dielectric layer so as to fill a remaining portion of the first portion of the trench and to fill the second portion of the trench so that a portion of the fifth dielectric layer filling the second portion of the trench contacts a portion of the third dielectric layer overlying the upper surface of the substrate and a portion of the conductive layer overlying the third dielectric layer.

10. The method of claim 9, wherein forming the fourth dielectric layer comprises:

filling the trench with the fourth dielectric layer to a level above the upper surface of the substrate; and

recessing the fourth dielectric layer so that the upper surface of the fourth dielectric layer is located below the upper surface of the substrate.

11. The method on claim 10 further comprises curing the fourth dielectric layer before recessing the fourth dielectric layer.

12. The method of claim 9, wherein forming the second dielectric layer comprises forming a portion of the second dielectric layer overlying an upper surface of the conductive layer.

13. The method of claim 12, wherein forming the portion of the second dielectric layer overlying the upper surface of the conductive layer comprises forming the second dielectric layer on an upper surface of a hard mask layer formed overlying the upper surface of the conductive layer.

14. The method of claim 9, wherein the third dielectric layer is a tunnel dielectric layer and the conductive layer is a floating gate layer, and further comprising after forming the fifth dielectric layer:

forming an intergate dielectric layer overlying the floating gate layer; and

forming a control gate overlying the intergate dielectric layer.