Methods of manufacture of vertical nanowire FET devices
First Claim
1. A method of forming a vertical Field Effect Transistor (FET) comprising:
- forming an FET device comprising an FET channel region located between a doped source region and a doped drain region in a vertical semiconductor nanowire with said doped source region and said doped drain region formed in distal ends of said vertical semiconductor nanowire aside from said channel region by the following steps;
forming a bottom source/drain electrode on a substrate;
forming a bottom spacer layer composed of a dielectric or insulating material on said bottom source/drain electrode;
forming a gate electrode layer or layers over said bottom spacer layer;
forming an upper spacer layer composed of a dielectric or insulating material over said gate electrode layer or layers with said upper spacer layer having a top surface;
creating a columnar pore extending down from said top surface through said upper spacer layer, said gate electrode layer or layers, and said bottom spacer layer to said bottom source/drain electrode;
then etching through said columnar pore to form a recessed notch or pocket in said gate electrode layer or layers;
then forming a conformal gate dielectric layer on surfaces of said columnar pore including said recessed pocket;
then etching back said conformal gate dielectric layer from said surfaces of said columnar pore, leaving said gate dielectric layer in said recessed notch or pocket in said gate electrode layer;
then filling said columnar pore with a semiconductor material by plating to form said vertical semiconductor nanowire therein having a bottom end formed on said bottom source/drain electrode; and
then forming a top source/drain electrode in contact with a top end of said vertical semiconductor nanowire.
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Abstract
A vertical Field Effect Transistor (FET) comprising a vertical semiconductor nanowire is formed by the following steps. Create a columnar pore in a bottom dielectric layer formed on a bottom electrode. Fill the columnar pore by plating a vertical semiconductor nanowire having a bottom end contacting the bottom electrode. Form a doped source region and a doped drain region in the vertical semiconductor nanowire thereby forming an FET device with a FET channel region between the source region and a drain region, which are formed in distal ends of the vertical semiconductor nanowire. Form a gate dielectric layer around the channel region of the vertical semiconductor nanowire. Then form a gate electrode around the gate dielectric layer. Form a top electrode contacting a top end of the vertical semiconductor nanowire.
83 Citations
9 Claims
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1. A method of forming a vertical Field Effect Transistor (FET) comprising:
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forming an FET device comprising an FET channel region located between a doped source region and a doped drain region in a vertical semiconductor nanowire with said doped source region and said doped drain region formed in distal ends of said vertical semiconductor nanowire aside from said channel region by the following steps; forming a bottom source/drain electrode on a substrate; forming a bottom spacer layer composed of a dielectric or insulating material on said bottom source/drain electrode; forming a gate electrode layer or layers over said bottom spacer layer; forming an upper spacer layer composed of a dielectric or insulating material over said gate electrode layer or layers with said upper spacer layer having a top surface; creating a columnar pore extending down from said top surface through said upper spacer layer, said gate electrode layer or layers, and said bottom spacer layer to said bottom source/drain electrode; then etching through said columnar pore to form a recessed notch or pocket in said gate electrode layer or layers; then forming a conformal gate dielectric layer on surfaces of said columnar pore including said recessed pocket; then etching back said conformal gate dielectric layer from said surfaces of said columnar pore, leaving said gate dielectric layer in said recessed notch or pocket in said gate electrode layer; then filling said columnar pore with a semiconductor material by plating to form said vertical semiconductor nanowire therein having a bottom end formed on said bottom source/drain electrode; and then forming a top source/drain electrode in contact with a top end of said vertical semiconductor nanowire. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification