ZnO based semiconductor devices and methods of manufacturing the same

• US 7,893,431 B2
• Filed: 04/17/2007
• Issued: 02/22/2011
• Est. Priority Date: 04/17/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, I-hun, Kang, Dong-hun, Park, Young-soo, Kim, Chang-jung
• Primary Examiner(s): Toledo; Fernando L
• Assistant Examiner(s): Dulka; John P
• Application Number:
  US11/785,269
• Publication Number:
  US 20070252147A1
• Time in Patent Office: 1,407 Days
• Field of Search: 257/43, 257/52, 257/57, 257/59, 257/72, 257/290, 257/324, 257/E33.004, 438/482, 438/483
• US Class Current: 257/43
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A semiconductor device may include a composite represented by Formula 1 below as an active layer.
x(Ga₂O₃)·y(In₂O₃)·z(ZnO)  Formula 1
wherein, about 0.75≦x/z≦ about 3.15, and about 0.55≦y/z≦ about 1.70.

Switching characteristics of displays and driving characteristics of driving transistors may be improved by adjusting the amounts of a gallium (Ga) oxide and an indium (In) oxide mixed with a zinc (Zn) oxide and improving optical sensitivity.

Claims

1. A semiconductor device comprising:

a substrate;

an active layer including a composite represented by Formula 1 below, on the substrate;

source and drain electrodes electrically connected to the active layer;

a gate electrode on the active layer; and

a gate insulating layer between the gate electrode and the active layer;

x(Ga₂O₃)·

y(In₂O₃)·

z(ZnO) 

 

Formula 1

wherein x, y, and z are about 1.25≦

x/z≦

about 1.45, and about 1.45≦

y/z≦

about 1.65 in Formula 1, and

wherein, when a drain current is 1E<sup>−

10</sup>A, the difference of V(light on) and V(light off) is equal to or less than 5 V.

2. The semiconductor device of claim 1, wherein the source and drain electrodes are formed of a metal oxide selected from the group consisting of tin-doped indium oxide (ITO), indium zinc oxide (IZO), and aluminum-doped zinc oxide (ZAO).

3. The semiconductor device of claim 1, wherein the source and drain electrodes include a metal selected from the group consisting of titanium (Ti), platinum (Pt), chromium (Cr), tungsten (W), aluminum (Al), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta) and an alloy thereof.

4. The semiconductor device of claim 3, wherein the source and drain electrodes are formed of a plurality of metal layers.

5. The semiconductor device of claim 3, wherein an n+ layer is formed between the source or drain electrode and the active layer.

6. The semiconductor device of claim 1, wherein the gate insulating layer includes a nitride, an oxide, or a high dielectric oxide.

7. The semiconductor device of claim 1, wherein the gate electrode includes a metal selected from the group consisting of titanium (Ti), platinum (Pt), chromium (Cr), tungsten (W), aluminum (Al), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta) and an alloy thereof.

8. The semiconductor device of claim 1, wherein the substrate is a glass substrate or a plastic substrate.

9. The semiconductor of claim 1, wherein the active layer is amorphous.

10. A method of manufacturing a semiconductor device, the method comprising:

forming an active layer including a composite represented by Formula 1 below, source and drain electrodes, a gate insulating layer and a gate electrode on a substrate,

x(Ga₂O₃)·

y(In₂O₃)·

z(ZnO) 

 

Formula 1

wherein x, y, and z are about 1.25≦

x/z≦

about 1.45 and about 1.45≦

y/z≦

about 1.65 in Formula 1, and

wherein, when a drain current is 1E<sup>−

10</sup>A, the difference of V(light on) and V(light off) is equal to or less than 5 V.

11. The method of claim 10, wherein the active layer is formed on the substrate, the source and drain electrodes are formed to be electrically connected to the active layer, the gate insulating layer is formed on the active layer, and the gate electrode is formed on the active layer.

12. The method of claim 10, wherein the gate electrode is formed on the substrate, the gate insulating layer is formed on the gate electrode, the active layer is formed on the gate insulating layer, and the source and drain electrodes are formed to be electrically connected to the active layer.

13. The method of claim 10, wherein the source and drain electrodes are formed of a metal oxide.

14. The method of claim 10, further comprising:

forming an n+ layer between the active layer and the source and drain electrodes. .

15. The method of claim 10, further comprising:

annealing the active layer and the source and drain electrodes, after forming the active layer and the source and drain electrodes.

16. The method of claim 15, wherein annealing is performed at a temperature of about 400°

or less in a nitrogen atmosphere.

17. The method of claim 10, wherein the active layer is amorphous.