MOS transistor with gate trench adjacent to drain extension field insulation

• US 7,893,499 B2
• Filed: 04/03/2009
• Issued: 02/22/2011
• Est. Priority Date: 04/04/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hu, Binghua, Seetharaman, Sridhar, Efland, Taylor Rice, Denison, Marie, Pendharkar, Sameer
• Primary Examiner(s): Pham; Thanh V
• Assistant Examiner(s): FERNANDES, ERROL V
• Application Number:
  US12/417,810
• Publication Number:
  US 20100252882A1
• Time in Patent Office: 690 Days
• Field of Search: 257/367, 257/299, 257/365, 257/366
• US Class Current: 257/367
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

Claims

1. An integrated circuit containing an MOS transistor, said integrated circuit comprising:

a semiconductor substrate;

a drift region formed in said substrate, said drift region having a first conductivity type, such that said drift region extends to a top surface of said substrate;

an isolation dielectric layer formed at said top surface of said substrate over said drift region;

a gate trench formed in said substrate, such that said gate trench abuts said isolation dielectric layer;

a body well formed in said substrate adjacent to said drift region, such that said body well overlaps a first portion of a bottom surface of said gate trench, and such that said body well has an opposite conductivity type from said drift region;

a gate dielectric layer formed on exposed surfaces of said substrate in said gate trench;

a gate formed on said gate dielectric layer in said gate trench; and

a source diffused region formed in said body well, such that said source diffused region abuts said gate dielectric layer in said gate trench and overlaps a second portion of said bottom surface of said gate trench, said second portion of said bottom surface of said gate trench being within said first portion of said bottom surface of said gate trench, and such that said source diffused region has a same conductivity type as said drift region.

2. The integrated circuit of claim 1, further including:

a second isolation dielectric layer formed at said top surface of said substrate over said drift region, such that said second isolation dielectric layer is separate from said first isolation dielectric layer; and

a second gate trench formed in said substrate such that;

said second gate trench is separate from said first gate trench;

said second gate trench abuts said second isolation dielectric layer;

said body well overlaps a first portion of a bottom surface of said second gate trench;

said gate dielectric layer is formed on exposed surfaces of said substrate in said second gate trench;

said gate is formed on said gate dielectric layer in said second gate trench; and

said source diffused region abuts said gate dielectric layer in said second gate trench and overlaps a second portion of said bottom surface of said second gate trench, said second portion of said bottom surface of said second gate trench being within said first portion of said bottom surface of said second gate trench.

3. The integrated circuit of claim 2, in which said gate overlaps said substrate between said first gate trench and said second gate trench.

4. The integrated circuit of claim 1, in which a lateral distance from a boundary of said source diffused region to a boundary of said body well is substantially constant on lateral surfaces and said bottom surface of said gate trench.

5. The integrated circuit of claim 1, in which a depth of said gate trench is less than a depth of said isolation dielectric layer.

6. The integrated circuit of claim 1, further including a field plate formed on a top surface of said isolation dielectric layer.