Semiconductor device including MISFET having internal stress film

• US 7,893,501 B2
• Filed: 07/09/2008
• Issued: 02/22/2011
• Est. Priority Date: 06/16/2003
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Tsutsui, Masafumi, Akamatsu, Kaori, Umimoto, Hiroyuki
• Primary Examiner(s): Weiss; Howard
• Application Number:
  US12/170,191
• Publication Number:
  US 20090050981A1
• Time in Patent Office: 958 Days
• Field of Search: 257/369
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.

Claims

1. A semiconductor device, comprising a MISFET, wherein

the MISFET includes:

an active region made of a semiconductor substrate;

a gate insulating film formed on the active region;

a gate electrode formed on the gate insulating film;

source/drain regions formed in regions of the active region located on both sides of the gate electrode; and

a silicon nitride film formed over from side surfaces of the gate electrode to upper surfaces of the source/drain regions, wherein;

the silicon nitride film is not formed on an upper surface of the gate electrode, and

the gate electrode protrudes upward from a surface level of parts of the silicon nitride film located at both side surfaces of the gate electrode.

2. The semiconductor device of claim 1, wherein

the silicon nitride film is for generating a stress in a substantially parallel direction to the gate length direction in a channel region located in the active region under the gate electrode.

3. The semiconductor device of claim 2, wherein

the substantially parallel direction of the stress includes a direction tilted by an angle of less than 10 degree from a direction in which carriers move.

4. The semiconductor device of claim 1, wherein

the silicon nitride film is directly in contact with the source/drain regions.

5. The semiconductor device of claim 1, wherein

the silicon nitride film is formed above the source/drain regions with a thin film interposed therebetween.

6. The semiconductor device of claim 1, wherein

the source/drain regions include lightly doped impurity regions formed in regions of the active region located on both sides of the gate electrode, heavily doped impurity regions formed in regions of the active region respectively extending outwardly from the lightly doped impurity regions to be in contact with the lightly doped impurity regions and having a higher impurity concentration than that of the lightly doped impurity regions, and a silicide layer.

7. The semiconductor device of claim 1, further comprising:

a sidewall formed on the side surface of the gate electrode, wherein

the silicon nitride film is formed over the side surfaces of the gate electrode with the sidewall interposed between the silicon nitride film and the side surface of the gate electrode.

8. The semiconductor device of claim 1, wherein

a principal surface of the semiconductor substrate is substantially a {100} plane, and

the gate length direction of the gate electrode is substantially a <

011>

direction.

9. The semiconductor device of claim 1, further comprising:

an interlevel insulating film formed on the silicon nitride film; and

a contact plug provided so as to pass through the interlevel insulating film and the silicon nitride film and to be connected to the source/drain regions.

10. The semiconductor device of claim 1, wherein:

the active region is divided by an isolation region formed in the semiconductor substrate, and

the silicon nitride film is formed to extend over the isolation region as well as the source/drain regions.

11. The semiconductor device of claim 10, wherein a lower surface of the isolation region is located in the semiconductor substrate and is in direct contact with the semiconductor substrate.

12. The semiconductor device of claim 1, wherein

the gate insulating film is a silicon oxide film.

13. The semiconductor device of claim 1, wherein

the gate insulating film is a silicon oxynitride film.

14. The semiconductor device of claim 1, wherein

the gate electrode has a polysilicon film.

15. The semiconductor device of claim 1, wherein

the gate electrode has a metal film.

16. The semiconductor device of claim 1, wherein

the silicon nitride film is provided so as to cover at least part of at least one of the source/drain regions.

17. The semiconductor device of claim 1, wherein

the silicon nitride film covers at least respective parts of the source/drain regions.

18. The semiconductor device of claim 1, wherein

the silicon nitride film covers at least respective parts of both side surfaces of the gate electrode.

19. The semiconductor device of claim 1, wherein

the MISFET is an nMISFET and

the source/drain regions are n-type source/drain regions.

20. The semiconductor device of claim 19, wherein

the silicon nitride film is for generating a tensile stress in a substantially parallel direction to the gate length direction in a channel region located in the active region under the gate electrode.

21. The semiconductor device of claim 19, wherein

the n-type source/drain regions include n-type lightly doped impurity regions, n-type heavily doped impurity regions and a silicide layer.

22. The semiconductor device of claim 1, wherein the silicon nitride film directly contacts with the side surfaces of the gate electrode.

23. The semiconductor device of claim 1, wherein

an upper surface of the gate electrode is higher than an upper surface of the parts of the silicon nitride film located at both side surfaces of the gate electrode.

24. The semiconductor device of claim 1, wherein

the gate insulating film is formed only under a lower surface of the gate electrode.

25. The semiconductor device of claim 1, further comprising:

a sidewall formed on the side surface of the gate electrode;

an interlevel insulating film formed on the silicon nitride film;

an isolation region formed in the semiconductor substrate to divide the active region; and

a contact plug provided so as to pass through the interlevel insulating film and the silicon nitride film and to be connected to the source/drain regions, wherein

the silicon nitride film is formed over the side surfaces of the gate electrode with the sidewall interposed between the silicon nitride film and the side surface of the gate electrode and to extend over the isolation region as well as the source/drain regions.