Metal oxide semiconductor (MOS) transistors with increased break down voltages and methods of making the same

• US 7,893,507 B2
• Filed: 01/16/2009
• Issued: 02/22/2011
• Est. Priority Date: 01/23/2008
• Status: Active Grant

• Current Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Original Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Inventors: Spenea, Marian Udrea, Lipcsei, Laszlo, Popescu, Serban Mihai
• Primary Examiner(s): Tran; Tan N
• Application Number:
  US12/321,258
• Publication Number:
  US 20090184380A1
• Time in Patent Office: 767 Days
• Field of Search: 257/401, 257/402, 257/409, 257/E29.255, 438/17, 438/163, 438/174
• US Class Current: 257/402
• CPC Class Codes: H01L 29/0688 characterised by the particular shape of a junction between semiconductor regions
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A transistor comprises a substrate of a first conductivity type, a drain region and a source region of a second conductivity type, a gate, a gate oxide layer, an adjustment implant region of the first conductivity type and a planar junction. The drain region and the source region are disposed in the substrate. The gate is placed over the substrate between the source region and the drain region. The gate is separated from the substrate by the gate oxide layer. The adjustment implant region is disposed under the gate oxide layer and in the substrate. A second doping concentration of the adjustment implant region is higher than a first doping concentration of the substrate. The adjustment implant region and the drain region in a predetermined shape form the planar junction with a surface curvature pointing towards the drain region to relax electrical field intensity at a location of the planar junction.

Claims

1. A transistor comprising:

a substrate of a first conductivity type and having a first doping concentration;

a drain region and a source region of a second conductivity type and disposed in said substrate;

a gate separated from said substrate by a gate oxide layer and placed between said source region and said drain region;

an adjustment implant region of said first conductivity type and disposed under said gate oxide layer and in said substrate, said adjustment implant region having a second doping concentration higher than said first doping concentration; and

a planar junction formed between said adjustment implant region and said drain region, said adjustment implant region and said drain region being in a predetermined shape to form said planar junction with a surface curvature pointing towards said drain region to relax electrical field intensity at a location of said planar junction.

2. The transistor of claim 1, wherein said drain region comprises a first well region and a second drain region disposed in said first well region, and wherein said first well region has a lighter doping concentration than said second drain region.

3. The transistor of claim 1, further comprising:

a bulk region of said first conductivity type disposed in said substrate.

4. The transistor of claim 1, wherein said predetermined shape is a substantially circular shape.

5. The transistor of claim 1, wherein said gate and said gate oxide layer are substantially circular in shape.

6. The transistor of claim 1, wherein said planar junction is substantially circular in shape.

7. The transistor of claim 1, wherein a thickness of said gate oxide layer is determined by a transconductance between said drain region and said source region.

8. The transistor of claim 1, wherein a peak of an electrical field at said drain region side of said planar junction is at a distance from said location of said planar junction.

9. The transistor of claim 8, wherein said distance between said peak of said electrical field and said location of said planar junction is determined by a drain voltage applied to said drain region.

10. The transistor of claim 1, wherein a breakdown voltage gain associated with said transistor is determined by a radius of said planar junction.

11. The transistor of claim 10, wherein said radius of said planar junction is no more than twice of an extension of a space charge region of said planar junction.

12. A method for fabricating a transistor, comprising:

providing a substrate of a first conductivity type and having a first doping concentration;

forming a source region and a drain region of a second conductivity type in said substrate;

placing a gate over said substrate and between said source region and said drain region;

separating said gate from said substrate by a gate oxide layer;

forming an adjustment implant region under said gate oxide layer and in said substrate, said adjustment implant region being of said first conductivity type and having a second doping concentration higher than said first doping concentration; and

forming a planar junction between said adjustment implant region and said drain region, said adjustment implant region and said drain region being in a predetermined shape to form said planar junction with a surface curvature pointing towards said drain region to relax electrical field intensity at a location of said planar junction.

13. The method of claim 12, further comprising:

forming a first well region in said drain region; and

forming a second drain region in said first well region, wherein said first well region has a lighter doping concentration than said second drain region.

14. The method of claim 12, further comprising:

forming a bulk region of said first conductivity type in said substrate.

15. The method of claim 12, wherein said predetermined shape is a substantially circular shape.

16. The method of claim 12, wherein said gate and said gate oxide layer are substantially circular in shape.

17. The method of claim 12, wherein said planar junction is substantially circular in shape.

18. The method of claim 12, further comprising:

determining a thickness of said gate oxide layer by a transconductance between said drain region and said source region.

19. The method of claim 12, wherein a peak of an electrical field at said drain region side of said planar junction is at a distance from said location of said planar junction.

20. The method of claim 19, further comprising:

determining said distance between said peak of said electrical field and said location of said planar junction by a drain voltage applied to said drain region.

21. The method of claim 12, further comprising:

determining a breakdown voltage gain associated with said transistor by a radius of said planar junction.

22. The method of claim 21, wherein said radius of said planar junction is no more than twice of an extension of a space charge region of said planar junction.