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Integrated circuit, memory module, and method of manufacturing an integrated circuit

  • US 7,893,511 B2
  • Filed: 07/17/2008
  • Issued: 02/22/2011
  • Est. Priority Date: 07/17/2008
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit, comprimising a plurity of magnetic tunneling junction stacks, each magnetic tunneling junction stack comprising a reference layer, a barrier layer and a free layer, wherein the plurality of magnetic tunneling junction stacks share a continuous common reference layer, wherein the free layers are laterally separated from each other, wherein a lateral electrical resistance of the continuous common reference layer between two neighboring magnetic tunneling junction stacks is higher than a vertical electrical resistance between a top surface of the continuous common reference layer and a bottom surface of the continuous common reference layer.

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