Integrated circuit, memory module, and method of manufacturing an integrated circuit

• US 7,893,511 B2
• Filed: 07/17/2008
• Issued: 02/22/2011
• Est. Priority Date: 07/17/2008
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Ruehrig, Manfred, Vieth, Michael, Klostermann, Ulrich
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US12/175,236
• Publication Number:
  US 20100013035A1
• Time in Patent Office: 950 Days
• Field of Search: 257/427, 257/421, 257/E43.001, 257/E43.006, 438/48, 365/158
• US Class Current: 257/427
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

Abstract

An integrated circuit includes a plurality of magnetic tunneling junction stacks, each magnetic tunneling junction stack including a reference layer, a barrier layer and a free layer, wherein the plurality of magnetic tunneling junction stacks share a continuous common reference layer.

Claims

1. An integrated circuit, comprimising a plurity of magnetic tunneling junction stacks, each magnetic tunneling junction stack comprising a reference layer, a barrier layer and a free layer, wherein the plurality of magnetic tunneling junction stacks share a continuous common reference layer, wherein the free layers are laterally separated from each other, wherein a lateral electrical resistance of the continuous common reference layer between two neighboring magnetic tunneling junction stacks is higher than a vertical electrical resistance between a top surface of the continuous common reference layer and a bottom surface of the continuous common reference layer.

2. The integrated circuit according to claim 1, wherein the continuous common reference layer has a reduced thickness between the magnetic tunneling junction stacks.

3. The integrated circuit according to claim 1, wherein the barrier layers together form a continuous common barrier layer shared by all magnetic tunneling junction stacks.

4. The integrated circuit according to claim 3, wherein a lateral electrical resistance of the continuous common barrier layer between two neighboring magnetic tunneling junction stacks is lower than a vertical electrical resistance between a top surface of the continuous common barrier layer and a bottom surface of the continuous common barrier layer.

5. The integrated circuit according to claim 1, wherein the free layers are laterally separated from each other by a material that is magnetically inactive or only weakly active.

6. The integrated circuit according to claim 5, wherein the free layers are laterally separated from each other by a material having a higher electrical resistance than the free layers.

7. The integrated circuit according to claim 1, wherein each memory cell comprises a select device.

8. The integrated circuit according to claim 1, wherein the free layers are electrically connected to a common conductive plate arranged above the magnetic tunneling junction stacks.

9. The integrated circuit according to claim 1, wherein a plurality of free layers is electrically connected to a common conductive line arranged above the magnetic tunneling junction stacks.

10. The integrated circuit according to claim 1, wherein the magnetic tunneling junction stacks serve as sensors.

11. The integrated circuit according to claim 1, wherein the magnetic tunneling junction stacks serve as memory elements.

12. A memory module comprising at least one integrated circuit comprising a plurality of magneto-resistive memory cells, each memory cell comprising a reference layer, a barrier layer and a free layer that are stacked above each other in this order, wherein the free layers are laterally separated from each other, wherein the reference layers together form a continuous common reference layer shared by all memory cells, and wherein a lateral electrical resistance of the continuous common reference layer between two neighboring magneto-resistive memory cells is higher than a vertical electrical resistance between a top surface of the continuous common reference layer and a bottom surface of the continuous common reference layer.

13. The memory module according to claim 12, wherein the memory module is stackable.