Power latch

• US 7,893,566 B2
• Filed: 03/13/2009
• Issued: 02/22/2011
• Est. Priority Date: 03/13/2009
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Stultz, Julie, Yarbrough, Roy L., Macaluso, Steven M.
• Primary Examiner(s): Fureman; Jared J
• Assistant Examiner(s): Amrany; Adi
• Application Number:
  US12/403,490
• Publication Number:
  US 20100231051A1
• Time in Patent Office: 711 Days
• Field of Search: 307 64- 66, 307/130
• US Class Current: 307/130
• CPC Class Codes: H03K 3/356 Bistable circuits

Abstract

A circuit that automatically, seamlessly connects the higher (or the lower) of two power supplies to an output is described. The circuit does not incur a one diode drop when the two power supplies are at about the same voltage levels, and the unused power supply draws no stand-by current. Cross coupled transistor and cross coupled inverters are employed.

Claims

1. A circuit that connects the higher voltage of two power supplies to an output, the circuit comprising:

a first transistor with its source connected to a first power supply and its gate to a second power supply;

a second transistor with its source connected to the second power supply and its gate to the first power supply;

cross coupled first and second inverters, the first inverter input connected to the first transistor drain and the second inverter input connected to the second transistor drain;

the first inverter powered by the second power supply and the second inverter powered by the first power supply;

the input of the first inverter connected to the output of the second inverter, and the input of the second inverter connected to the output of the first inverter;

a third transistor with its gate connected to the drain of the second transistor, its source connected to the first power supply and its drain connected to the output voltage; and

a fourth transistor with its gate connected to the first transistor drain, its source connected to the second power supply and its drain connected to the output.

2. The circuit of claim 1, where the power supply connections from the third and the fourth transistors are switched and the power supply connections of the first and second inverters are switched, wherein the circuit now outputs the lower of the two power supplies rather than the higher.

3. A method for connecting the higher of two power supplies to an output voltage, the method comprising:

connecting a first transistor source to a first power supply and its gate to a second power supply;

connecting a second transistor source to the second power supply and its gate to the first power supply;

cross-coupling first and second inverters, the first inverter input connected to the first transistor drain and the second inverter input connected to the second transistor drain;

the first inverter powered by the second power supply and the second inverter powered by the first power supply;

the input of the first inverter connected to the output of the second inverter, and the input of the second inverter connected to the output of the first inverter;

connecting a third transistor gate to the drain of the second transistor, its source connected to the first power supply and its drain connected to the output voltage; and

connecting a fourth transistor gate to the first transistor drain, its source connected to the second power supply and its drain connected to the output voltage.

4. The method of claim 3, switching the power supply connections of the third and the fourth transistors and the power supply connections of the first and second inverters, wherein the circuit now outputs the lower of the two power supplies rather than the higher.