Method and circuit for rapid alignment of signals

• US 7,893,724 B2
• Filed: 11/13/2007
• Issued: 02/22/2011
• Est. Priority Date: 03/25/2004
• Status: Expired due to Fees

• Current Assignee: RPX Corporation
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Moyal, Nathan, Stiff, Jonathon
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): O'Neill, Patrick
• Application Number:
  US11/985,340
• Publication Number:
  US 20080136470A1
• Time in Patent Office: 1,197 Days
• Field of Search: 327 1- 12, 327/141, 327/144, 327152-154, 327161-163, 327/298, 327/299
• US Class Current: 327/12
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03K 5/156 Arrangements in which a continuous pulse train is transformed into a train having a desired pattern

Abstract

Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.

Claims

1. A circuit for aligning two or more signals including a first and a shifted copy of a second signal, the circuit comprising:

a first gate coupled to a first delay block, the first gate configured for receiving the first signal and a power down signal;

a second gate coupled to a second delay block, the second gate configured for receiving a shifted copy of the second signal and the power down signal;

a first flip-flop configured for receiving the first signal and an output from the second delay block;

a second flip-flop configured for receiving the shifted copy of the second signal and an output from the first delay block;

a third gate configured for receiving an output from the first flip-flop and an output from the second flip-flop; and

a fourth gate configured for receiving an output from the third gate and the power down signal and providing a circuit output signal.

2. The circuit of claim 1, wherein the circuit output signal comprises an alignment detection signal.

3. The circuit of claim 1, wherein the circuit output signal is high when the first signal and the shifted copy of the second signal are substantially aligned.

4. The circuit of claim 1, wherein the circuit output signal is low when the first signal and the shifted copy of the second signal are not substantially aligned.

5. The circuit of claim 1, wherein the circuit output signal is low when the power down signal is low.

6. The circuit of claim 1, wherein the circuit comprises a phase detector.

7. The circuit of claim 6, wherein one or more phase detectors are configured to be connected in parallel.

8. The circuit of claim 7, wherein a detection of alignment between the first signal and the shifted copy of the second signal in one phase detector is configured to cause each of the phase detectors connected in parallel to power down.

9. The circuit of claim 1, wherein the circuit is coupled to a shift register.

10. The circuit of claim 9, wherein the shift register is configured to deactivate outputs that are not aligned with the first signal.