High frequency switch circuit having reduced input power distortion

• US 7,893,749 B2
• Filed: 12/19/2008
• Issued: 02/22/2011
• Est. Priority Date: 01/22/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Honda, Yuri
• Primary Examiner(s): Wells; Kenneth B.
• Application Number:
  US12/318,019
• Publication Number:
  US 20090184747A1
• Time in Patent Office: 795 Days
• Field of Search: 327/365, 327/415, 327/430, 333101-103
• US Class Current: 327/365
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

There has been a problem that the distortion characteristic of a switch circuit for a high frequency is deteriorated. A switch circuit in accordance with one aspect of the present invention includes a transistor connected in series between input and output terminals, a control terminal that receives a signal to control the conductive state of the transistor, a first resistor connected between the control electrode of the transistor and the control terminal, and a series circuit of a diode and a second resistor, the series circuit being connected in parallel with the first resistor between the control terminal and the control electrode of the transistor.

Claims

1. A switch circuit, comprising:

a first transistor connected in series between input and output terminals;

a control terminal that receives a signal to control a conductive state of the transistor;

a first resistor connected between a control electrode of the transistor and the control terminal; and

a series circuit comprising;

a first diode and a second resistor, the series circuit being connected in parallel with the first resistor between the control terminal and the control electrode of the transistor, and

a second diode serially connected to said first diode.

2. The switch circuit according to claim 1, wherein an anode of the first diode is connected on a control terminal side and a cathode of the first diode is connected on a control electrode side.

3. The switch circuit according to claim 1, wherein an anode of the first diode is connected on a control electrode side and a cathode of the first diode is connected on a control terminal side.

4. The switch circuit according to claim 1, wherein:

a plurality of the series circuits is connected in parallel;

at least one of the series circuits comprises a first diode, an anode of the first diode being connected on a control terminal side and a cathode of the first diode being connected on a control electrode side; and

at least another one of the series circuits comprises a second diode, an anode of the second diode being connected on the control electrode side and a cathode of the second diode being connected on the control terminal side.

5. The switch circuit according to claim 1, further comprising a second transistor,

wherein the first transistor and the second transistor are connected in series between the input and output terminals.

6. The switch circuit according to claim 1, further comprising a third resistor, one end of the third resistor being connected to the control electrode of the first transistor and an other end of the third resistor being connected to the first resistor and the series circuit.

7. The switch circuit according to claim 6, further comprising:

a second transistor; and

a fourth resistor, one end of the fourth resistor being connected to control electrode of the second transistor and an other end of the fourth resistor connected to the first resistor and the series circuit.

8. The switch circuit according to claim 1, further comprising a bias supply resistor that connects a source and a drain of the first transistor.

9. The switch circuit according to claim 1, wherein the second resistor is connected between the second diode and the control electrode of the first transistor.

10. A switch circuit, comprising:

a transistor having a source associated with a first node, a drain associated with a second node, and a control electrode associated with a third node;

an input terminal associated with the first node;

an output terminal associated with the second node;

a control terminal associated with a fourth node;

a first resistor provided between the third node and fourth node; and

a series circuit associated with the third node, said series circuit comprising;

a second resistor provided between the third node and fourth node and in parallel with the first resistor;

a first diode provided between the third node and fourth, node, said first diode being provided in parallel with the first resistor and in series with the second resistor; and

a second diode provided between the third node and fourth node and in parallel with the first resistor and in series with the first diode.

11. The switch circuit according to claim 10, further comprising a bias supply resistor arranged between the first node and the second node and in parallel with the transistor.

12. A semiconductor device, comprising:

an input terminal;

an output terminal;

a plurality of switch circuits, said plurality of switch circuits being provided in series between the input port and the output port, each of said switch circuits comprising;

a transistor having a source associated with a first node, a drain associated with a second node, and a control electrode associated with a third node;

an input terminal associated with the first node;

an output terminal associated with the second node;

a control terminal associated with a fourth node; and

a first resistor provided between the third node and fourth node; and

a plurality of series circuits associated with a respective third node of a respective one of the plurality of switch circuits, each of said series circuits comprising;

a second resistor provided between the third node and fourth node and in parallel with the first resistor;

a first diode provided between the third node and fourth node, said first diode being provided in parallel with the first resistor and in series with the second resistor; and

a second diode provided between the third node and fourth node and in parallel with the first resistor and in series with the first diode,

wherein, in a first switch circuit of the plurality of switch circuits, said first node is associated the input terminal of the semiconductor device,

wherein, in a final switch circuit of the plurality of switch circuits, said second node is associated the output terminal of the semiconductor device, and

wherein, in between respective consecutive switch circuits of the plurality of switch circuits, a respective second node is associated with a first node of a following switch circuit.

13. The semiconductor device according to claim 12, wherein each of the plurality of switch circuits further comprises a bias supply resistor arranged between the first node and the second node and in parallel with the transistor.

14. The semiconductor device according to claim 12, wherein said fourth node is associated with said control terminal of the plurality of switch circuits in parallel.

15. A semiconductor device, comprising:

an input terminal;

an output terminal;

a control terminal associated with a fourth node;

a plurality of switch circuits, said plurality of switch circuits being provided in series between the input port and the output port, each of said switch circuits comprising;

a transistor having a source associated with a first node, a control electrode, and a drain associated with a second node;

an input terminal associated with the first node; and

an output terminal associated with the second node;

a third node being connected in common with one end of each control electrode resistor, the other end of each control electrode resistor being connected to each control electrode of each transistor of said plurality of switch circuits;

a first resistor provided between the third node and the fourth node; and

a series circuit associated with the third node, said series circuit comprising;

a second resistor provided between the third node and fourth node and in parallel with the first resistor;

a first diode provided between the third node and fourth node, said first diode being provided in parallel with the first resistor and in series with the second resistor; and

a second diode provided between the third node and fourth node and in parallel with the first resistor and in series with the first diode.

16. The semiconductor device according to claim 15, wherein, in a first switch circuit of the plurality of switch circuits, said first node is associated with the input terminal of the semiconductor device,

wherein, in a final switch circuit of the plurality of switch circuits, said second node is associated the output terminal of the semiconductor device, and

wherein, in between respective consecutive switch circuits of the plurality of switch circuits, a respective second node is associated with a first node of a following switch circuit.