Quadrature modulator and calibration method
First Claim
1. A synchronous envelope detector, comprising:
- a) a Gilbert cell having at least one differential transistor pair in an upper tree and at least one transistor in a lower tree, the upper and lower trees interconnected and each of the upper and lower branches having input terminals;
b) a resistor divider network connected between the input terminals of the upper tree and the input terminals of the lower tree, the resistive values of the network selected such that a selected input signal having a signal level sufficient to saturate the at least one transistor pair of the upper tree is attenuated so as to not saturate the at least one transistor pair of the lower tree; and
c) a low pass filter connected to the upper tree, with an output signal of the detector provided to the low pass filter.
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Abstract
A quadrature modulator and a method of calibrating same by applying a first test tone signal to an in-phase modulation branch input of the modulator and a ninety degree phase-shifted version of the first test tone signal to a quadrature modulation branch input of the modulator. The carrier leakage level in an output signal of the modulator is measured and in response base band dc offset voltages are adjusted to minimize the carrier leakage. A second test tone signal is applied to the in-phase modulation branch input and a ninety degree phase-shifted version of the second test tone signal to the quadrature modulation branch input. The level of an undesired upper sideband frequency component in the output signal is measured and in response base band gains the in-phase and quadrature modulation branches and a local oscillator phase error are adjusted to minimize the undesired side band.
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Citations
15 Claims
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1. A synchronous envelope detector, comprising:
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a) a Gilbert cell having at least one differential transistor pair in an upper tree and at least one transistor in a lower tree, the upper and lower trees interconnected and each of the upper and lower branches having input terminals; b) a resistor divider network connected between the input terminals of the upper tree and the input terminals of the lower tree, the resistive values of the network selected such that a selected input signal having a signal level sufficient to saturate the at least one transistor pair of the upper tree is attenuated so as to not saturate the at least one transistor pair of the lower tree; and c) a low pass filter connected to the upper tree, with an output signal of the detector provided to the low pass filter. - View Dependent Claims (2, 3)
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4. A circuit, comprising:
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a first and second differential pair of transistors arranged in a first tree; a pair of transistors forming a second tree, the second tree coupled to the first tree, each of the first and second trees having input terminals; a low pass filter network coupled to the first tree; and a resistor divider network coupled between the input terminals of the first tree and the input terminals of the second tree, the resistor divider network having resistive values selected such that an input signal having a signal level sufficient to saturate the first and second differential transistor pairs of the first tree is attenuated so as not to saturate the first and second pair of transistors in the second tree. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12)
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13. A synchronous envelope detector, comprising:
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a) a Gilbert cell having at least one differential transistor pair in an upper tree and at least one transistor in a lower tree, the upper and lower trees interconnected and each of the upper and lower branches having input terminals; b) a resistor divider network connected between the input terminals of the upper tree and the input terminals of the lower tree, the resistive values of the network selected such that a selected input signal having a signal level sufficient to saturate the at least one transistor pair of the upper tree is attenuated so as to not saturate the at least one transistor pair of the lower tree; and c) a low pass filter connected to the upper tree, with an output signal of the detector provided to the low pass filter. - View Dependent Claims (14, 15)
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Specification