Quadrature modulator and calibration method

• US 7,893,758 B2
• Filed: 06/15/2009
• Issued: 02/22/2011
• Est. Priority Date: 04/24/2003
• Status: Expired due to Term

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: ST-Ericcson SA (Telefonaktiebolaget LM Ericsson)
• Inventors: Parsa, Ali, Faghfuri, Ali, Riou, Emmanuel, Hahn, Wilhelm Steffen, Fotowat-Ahmady, Ali, Jenabi, Mahta
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US12/484,544
• Publication Number:
  US 20090267701A1
• Time in Patent Office: 617 Days
• Field of Search: 329/347, 329/358, 329/362, 332103-105
• US Class Current: 329/362
• CPC Class Codes: H03C 3/406 using a feedback loop containing mixers or demodulators
• CPC Class Codes: H04L 27/364 Arrangements for overcoming imperfections in the modulator, e.g. quadrature error or unbalanced I and Q levels

Abstract

A quadrature modulator and a method of calibrating same by applying a first test tone signal to an in-phase modulation branch input of the modulator and a ninety degree phase-shifted version of the first test tone signal to a quadrature modulation branch input of the modulator. The carrier leakage level in an output signal of the modulator is measured and in response base band dc offset voltages are adjusted to minimize the carrier leakage. A second test tone signal is applied to the in-phase modulation branch input and a ninety degree phase-shifted version of the second test tone signal to the quadrature modulation branch input. The level of an undesired upper sideband frequency component in the output signal is measured and in response base band gains the in-phase and quadrature modulation branches and a local oscillator phase error are adjusted to minimize the undesired side band.

Claims

1. A synchronous envelope detector, comprising:

a) a Gilbert cell having at least one differential transistor pair in an upper tree and at least one transistor in a lower tree, the upper and lower trees interconnected and each of the upper and lower branches having input terminals;

b) a resistor divider network connected between the input terminals of the upper tree and the input terminals of the lower tree, the resistive values of the network selected such that a selected input signal having a signal level sufficient to saturate the at least one transistor pair of the upper tree is attenuated so as to not saturate the at least one transistor pair of the lower tree; and

c) a low pass filter connected to the upper tree, with an output signal of the detector provided to the low pass filter.

2. The detector of claim 1, wherein the lower branch has two BJT transistors, and a resistor is connected between emitters of the two BJT transistors.

3. The detector of claim 1, comprising a circuit for biasing the at least one transistor pair of the upper tree.

4. A circuit, comprising:

a first and second differential pair of transistors arranged in a first tree;

a pair of transistors forming a second tree, the second tree coupled to the first tree, each of the first and second trees having input terminals;

a low pass filter network coupled to the first tree; and

a resistor divider network coupled between the input terminals of the first tree and the input terminals of the second tree, the resistor divider network having resistive values selected such that an input signal having a signal level sufficient to saturate the first and second differential transistor pairs of the first tree is attenuated so as not to saturate the first and second pair of transistors in the second tree.

5. The circuit of claim 4, wherein an output signal of the envelope detector is provided to the low pass filter network.

6. The circuit of claim 4, wherein the pair of transistors in the second tree comprises two BJT transistors, and the second tree comprises a resistor coupled between emitter terminals of the two BJT transistors.

7. The circuit of claim 4, comprising a biasing circuit for biasing the first and second differential pairs of transistors in the first tree.

8. The circuit of claim 4, further comprising a quadrature modulator, the modulator comprising:

a) an in-phase modulation branch receiving as an input an analog in-phase base band signal, the in-phase modulation branch including a first dc offset adjustment circuit, a first base band gain adjustment circuit, and a first mixer;

b) a quadrature modulation branch receiving as an input an analog quadrature based band signal, the quadrature modulation branch including a second dc offset adjustment circuit, a second base band gain adjustment circuit, and a second mixer;

c) a local oscillator means for providing a local oscillator signal to the first mixer and a phase shifted version of the local oscillator signal to the second mixer;

d) a summer for summing the outputs of the first and second mixers;

e) an envelope detector for detecting an output signal of the modulator and providing a signal representative of the amplitude of the output signal of the quadrature modulator;

f) a band pass filter for filtering the amplitude signal; and

g) a signal strength indicator circuit for measuring the strength of the filtered amplitude signal, the indicator circuit providing a compensation signal for adjusting the phase shift of the local oscillator and the dc offsets and base band gains of the in-phase and quadrature base band signals.

9. The modulator according to claim 8, wherein the envelope detector comprises a synchronous detector and the signal strength indicator comprises a log indicator.

10. The modulator according to claim 9, comprising a programmable attenuator for adjusting the level of the output signal of the quadrature modulator, and wherein the envelope detector measures the output signal following attenuation.

11. The modulator according to claim 8, including a tone generator for supplying a test tone signal to the in-phase modulation branch input and a ninety degree phase-shifted version of the test tone signal to the quadrature modulation branch input.

12. The modulator according to claim 11, further comprising a circuit structured to:

a) apply a first test tone signal to the in-phase modulation branch input and a ninety degree phase-shifted version of the first test tone signal to the quadrature modulation branch input;

b) employ the compensation signal to minimize carrier leakage in the output signal by adjusting the base band dc offsets in the in-phase and quadrature branches;

c) apply a second test tone signal to the in-phase modulation branch input and a ninety degree phase-shifted version of the second test tone signal to the quadrature modulation branch input, wherein the second test tone has a frequency that is substantially one half of the frequency of the first test tone; and

d) employ the compensation signal to minimize an undesired upper sideband frequency component in the output signal by adjusting the base band gains the in-phase and quadrature modulation branches and the phase shift of the local oscillator signal.

13. A synchronous envelope detector, comprising:

a) a Gilbert cell having at least one differential transistor pair in an upper tree and at least one transistor in a lower tree, the upper and lower trees interconnected and each of the upper and lower branches having input terminals;

b) a resistor divider network connected between the input terminals of the upper tree and the input terminals of the lower tree, the resistive values of the network selected such that a selected input signal having a signal level sufficient to saturate the at least one transistor pair of the upper tree is attenuated so as to not saturate the at least one transistor pair of the lower tree; and

c) a low pass filter connected to the upper tree, with an output signal of the detector provided to the low pass filter.

14. The detector of claim 13, comprising a log detector structured to measure the amplitude of the filtered, spectrum-shifted signal, the log detector further structured to generate a compensation signal to minimize the LO feed through or undesired sideband.

15. The circuit of claim 14, wherein the detector comprises an attenuation circuit that selectively attenuates the output signal prior to a measurement of the output signal.