Non-volatile memory device and operation method of the same

• US 7,894,265 B2
• Filed: 04/18/2008
• Issued: 02/22/2011
• Est. Priority Date: 10/05/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoon, Tae-eung, Park, Yoon-dong, Kim, Won-joo, Lee, Tae-hee, Kim, Suk-pil, Koo, June-mo
• Primary Examiner(s): HUR, JUNG H
• Application Number:
  US12/081,679
• Publication Number:
  US 20090091975A1
• Time in Patent Office: 1,040 Days
• Field of Search: 365/185.05, 365/185.06, 365/185.11, 365/185.13, 365/185.17, 365/185.18
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor. A method of programming a target cell of the memory device includes activating selection transistors connected to a main string and substring of the target cell.

Claims

1. A non-volatile memory device comprising:

one or more main strings each including first and second substrings separately including a plurality of memory cell transistors;

a bit line; and

a charge supply line configured to provide charges to or block charges from the first and second substrings of each of the main strings,

wherein each of the main strings includes

a first transistor connected to the first substring,

a second transistor connected to the first transistor,

a third transistor connected to the second substring, and

a fourth transistor connected to the third transistor, and

wherein the bit line is electrically connected to gates of at least one of the first and second transistors, and at least one of the third and fourth transistors.

2. The non-volatile memory device of claim 1, wherein

the first transistor is a first ground selection transistor,

the second transistor is a first substring selection transistor,

the third transistor is a second ground selection transistor, and

the fourth transistor is a second substring selection transistor.

3. The non-volatile memory device of claim 2, further comprising:

a first substring selection line which is connected to a gate of the first substring selection transistor; and

a second substring selection line which is connected to a gate of the second substring selection transistor.

4. The non-volatile memory device of claim 3, further comprising:

a first dummy substring selection transistor which is connected between the first ground selection transistor and the first substring selection transistor, and includes a gate connected to the second substring selection line; and

a second dummy substring selection transistor which is connected to the second substring selection transistor, and includes a gate connected to the first substring selection line.

5. The non-volatile memory device of claim 2, further comprising:

a ground selection line which is connected to gates of the first and second ground selection transistors.

6. The non-volatile memory device of claim 5,

wherein the ground selection line is connected to the bit line.

7. The non-volatile memory device of claim 2, wherein the bit line is shared by the first and second substrings of each of the main strings.

8. The non-volatile memory device of claim 2, wherein the charge supply line is a common source line.

9. The non-volatile memory device of claim 2, further comprising:

a first string selection transistor which is connected to the first substring; and

a second string selection transistor which is connected to the second substring.

10. The non-volatile memory device of claim 2, wherein source and drain regions are formed on a semiconductor substrate between memory cell transistors, from among the plurality of memory cell transistors, by fringe fields.

11. The non-volatile memory device of claim 10, wherein the fringe fields are formed by applying voltages to gates of memory cell transistors from among the plurality of memory cell transistors.

12. The non-volatile memory device of claim 2, wherein the first and second substrings form flash memory having a perpendicular structure.

13. The non-volatile memory device of claim 1, wherein

the first transistor is a first substring selection transistor,

the second transistor is a first ground selection transistor,

the third transistor is a second substring selection transistor, and

the fourth transistor is a second ground selection transistor.

14. The non-volatile memory device of claim 13, further comprising:

a ground selection line which is connected to gates of the first and second ground selection transistors;

a first substring selection line which is connected to a gate of the first substring selection transistor; and

a second substring selection line which is connected to a gate of the second substring selection transistor.

15. A method of programming a target memory cell transistor of the non-volatile memory device of claim 1, the method comprising:

turning on first and second ground selection transistors connected to a main string including the target memory cell transistor;

turning on a substring selection transistor connected to a substring including the target memory cell transistor; and

turning off another substring selection transistor connected to another substring not including the target memory cell transistor.

16. The method of claim 15, wherein third and fourth ground selection transistors connected to another main string not including target memory cell transistor are turned off in order to inhibit programming of the other main string.

17. The method of claim 15, wherein a ground voltage is applied to a charge supply line.

18. The method of claim 15, wherein a program voltage is applied to the target memory cell transistor and a pass voltage is applied to other memory cell transistors, and

wherein the pass voltage turns on a memory cell transistor and the program voltage is higher than the pass voltage.

19. The method of claim 18, wherein a ground voltage is applied to memory cell transistors which are not disposed between the target memory cell transistor and the first or second ground selection transistors, or the memory cell transistors are floated.

20. A method of reading a target memory cell transistor of the non-volatile memory device of claim 1, the method comprising:

turning on first and second ground selection transistors connected to a main string including the target memory cell transistor;

turning on a substring selection transistor connected to a substring including the target memory cell transistor; and

turning off another substring selection transistor connected to another substring not including the target memory cell transistor.

21. The method of claim 20, wherein a ground voltage is applied to a charge supply line.

22. The method of claim 20, wherein a read voltage is applied to the target memory cell transistor and a pass voltage is applied to other memory cell transistors, and

wherein the pass voltage turns on a memory cell transistor and the read voltage turns on or off the target memory cell transistor in accordance with a threshold voltage level of the target memory cell transistor.