Adaptive play-out buffers and adaptive clock operation in packet networks

• US 7,894,489 B2
• Filed: 06/12/2006
• Issued: 02/22/2011
• Est. Priority Date: 06/10/2005
• Status: Active Grant

• Current Assignee: Microsemi Frequency And Time Corporation
• Original Assignee: Symmetricom Incorporated (Microchip Technology Incorporated)
• Inventors: Shenoi, Kishan
• Primary Examiner(s): Ahmed; Salman
• Application Number:
  US11/451,653
• Publication Number:
  US 20070041324A1
• Time in Patent Office: 1,716 Days
• Field of Search: 370/516, 370/429
• US Class Current: 370/516
• CPC Class Codes: G06F 5/14 for overflow or underflow handling, e.g. full or empty flags
• CPC Class Codes: H04J 3/0632 Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES] queuing arrangements in packet switching elements H04L49/90; synchronising systems for the synchronous transmission of a pulse code modulated video signal with one or more other pulse code modulated signals H04N7/56
• CPC Class Codes: H04L 7/005 Correction by an elastic buffer

Abstract

Methods and apparatus for a play-out buffer that may adjust offsets between clocks of two ends of a network link with an adaptive play-out buffer and adaptive clock control. The play-out buffer is a circular jitter buffer that permits the absorption of a frequency offset using controlled slips between two nodes of a network. The play-out buffer also accommodates some wander introduced by the time-delay variation across the network. The adaptive clock control reduces the frequency offset between the clocks of the two nodes. In this manner, even though some offsets between two nodes would render communication inefficient, embodiments of the present invention allow the effects of these offsets to be mitigated, thus providing for a better quality coupling.

Claims

1. A non-transitory computer-readable storage medium comprising computer executable instructions for carrying out the steps of:

setting a timer;

writing a data packet into a jitter buffer at a write address specified by a write address generator;

incrementing the write address generator;

reading a data packet from the jitter buffer at a current read address specified by a read address generator;

conditionally incrementing the read address generator based on;

(i) a current value of the timer, (ii) threshold address difference values T1 and T2, where T2>

T1, and (iii) a difference Δ

n between the write address specified by the write address generator and the current read address specified by the read address generator;

conditionally performing a controlled slip based on the current value of the timer, the threshold address difference values and the difference Δ

n; and

resetting the jitter buffer and the timer if the difference Δ

n is 0.

2. The non-transitory computer-readable medium of claim 1, wherein the jitter buffer is a dual-port RAM device.

3. The non-transitory computer-readable medium of claim 1, wherein the jitter buffer is organized as a modulo-2N circular buffer.

4. The non-transitory computer-readable storage medium of claim 1, wherein the read address generator is incremented if |Δ

n|>

T2, or if |Δ

n|>

0 and the timer has not expired.

5. The non-transitory computer-readable storage medium of claim 1, wherein the controlled slip is performed if T2≧

|Δ

n|>

0 and the timer has expired.

6. The non-transitory computer-readable storage medium of claim 5, wherein the controlled slip is performed by incrementing the read address generator zero times if Δ

n>

0 and incrementing the read address generator two times if Δ

n<

0.

7. The non-transitory computer-readable storage medium of claim 5, further comprising:

signaling a need for packet loss concealment if T1≧

|Δ

n|>

0 and the timer has expired.

8. The non-transitory computer-readable storage medium of claim 1, wherein the values for T2 and T1 are (½

)N and (¼

)N respectively, where 2N is the size of the jitter buffer.

9. A non-transitory computer-readable storage medium comprising computer executable instructions for carrying out the steps of:

writing a data packet into a jitter buffer at a write address specified by a write address generator;

incrementing the write address generator;

reading a data packet form the jitter buffer from a current read address specified by a read address generator;

setting a timer;

setting a flag for the data packet; and

generating a new read address based on a difference Δ

n between the write address specified by the write address generator and the current read address specified by the read address generator by carrying out one of the following actions;

if |Δ

n|>

T3, incrementing the read address generator;

if T3≧

|Δ

n|>

T2, checking the flag and the timer and, if the flag is true and the timer has expired, performing a controlled slip, or else, incrementing the read address generator;

if T2≧

|Δ

n|>

T1, checking the timer and, if the timer has expired, performing a controlled slip, or else, incrementing the read address generator;

if T1≧

|Δ

n|>

0, checking the timer and, if the timer has expired, performing a controlled slip and signaling a need for packet loss concealment, or else, incrementing the read address generator; and

if Δ

n is 0, resetting the jitter buffer by re-centering and resetting the timer,

wherein T1, T2, and T3 are threshold address difference values.

10. The non-transitory computer-readable storage medium of claim 9, wherein the values for T3, T2, and T1 are (¾

)N, (½

)N, and (¼

)N respectively, where 2N is the size of the jitter buffer.

11. The non-transitory computer-readable storage medium of claim 9, wherein the values for T3, T2, and T1 are (⅞

)N, (¾

)N, and (⅛

)N respectively, where 2N is the size of the jitter buffer.

12. The non-transitory computer-readable storage medium of claim 9, wherein the controlled slip is performed by incrementing the read address generator zero times if Δ

n>

0 and incrementing the read address generator two times if Δ

n<

0.