Devices and methods for sharing common target device with two different hosts according to common communication protocol

• US 7,895,387 B1
• Filed: 09/27/2007
• Issued: 02/22/2011
• Est. Priority Date: 09/27/2007
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Khodabandehlou, Hamid, Raza, Syed Babar, Lewis, Michael, Swindle, Scott
• Primary Examiner(s): Rinehart, Mark
• Assistant Examiner(s): Cerullo, Jeremy S
• Application Number:
  US11/904,758
• Time in Patent Office: 1,244 Days
• Field of Search: 710/316, 710/11, 710/305, 710/306, 710/315
• US Class Current: 710/316
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A controller circuit provides communication paths between multiple host devices and a target device. The controller circuit includes a first host idle detection circuit that determines when a first host interface (I/F) is in an idle state, an idle state being when the first host I/F is not communicating with the controller circuit. A switch circuit can selectively enables a controllable communication path between a second host I/F and a target device I/F. A first response circuit can be coupled to the first host I/F and output predetermined responses from the first host I/F in response to communications received on the first host I/F. The first response circuit outputting a predetermined response when at least the controller circuit has enabled the controllable communication path between a second host I/F and the target device I/F and disabled the controllable communication path between the first host I/F and the target device I/F.

Claims

1. A controller circuit, comprising:

a first host idle detection circuit configured to determine when a first host interface (I/F) is in an idle state, the idle state being when the first host I/F is not communicating with the controller circuit;

a switch controller circuit configured to enable communication paths between the first host I/F, a second host I/F, and a target device I/F; and

a first response circuit coupled to the first host I/F and configured to;

output a response when the controller circuit has enabled the communication path between the second host I/F and the target device I/F,

disable the communication path between the first host I/F and the target device I/F when the first host I/F is in the idle state and a target device is being accessed via the second host I/F, and

respond to communications received via the first host I/F while the target device is being accessed via the second host I/F,

wherein the first host I/F is configured to communicate with the switch controller circuit using a first communication protocol, the second host I/F is configured to communicate with the switch controller circuit using a second different communication protocol, and the target device I/F is configured to communicate with the switch controller circuit using a universal serial bus (USB) protocol.

2. The controller circuit of claim 1, further comprising:

a format circuit configured to generate communication tokens in response to requests from the second host I/F, each communication token corresponding to at least one communication protocol and including a type field indicating a type of communication.

3. The controller circuit of claim 2, wherein:

the type field indicates a communication direction between the second host I/F and the target device I/F, and each communication token further includes an endpoint field that identifies a memory location.

4. The controller circuit of claim 1, further comprising:

a second response circuit coupled to the second host I/F and configured to;

output responses from the second host I/F in response to communications received by the second host I/F, and

output responses when the controller circuit has enabled the communication path between the first host I/F and the target device I/F and disabled the communication path between the second host I/F and the target device I/F.

5. The controller circuit of claim 4, wherein:

the responses output by the first response circuit comply with the first communication protocol and the responses output by the second response circuit comply with the second communication protocol.

6. The controller circuit of claim 1, wherein:

the first response circuit is configured to respond to at least one of the communications received via the first host I/F by outputting a stall response or no acknowledge (NAK) response by the first I/F while the target device is being accessed via the second host I/F.

7. The controller circuit of claim 1, further comprising:

a plurality of endpoint storage locations coupled to the first host I/F, the second host I/F, and the target device I/F by the communication paths.

8. A method comprising:

determining whether a first host device is accessing a target device using a first communications protocol;

blocking access to the target device from the first host device when the first host device is not accessing the target device and a second host device is accessing the target device, while continuing to respond to communications received from the first host device requesting to access the target device;

receiving a token from the second host device, the token indicating a communications endpoint, a communications direction, and a second communications protocol; and

establishing communications between the second host device and the target device using the communications endpoint, the communications direction, and the second communications protocol, wherein the second communications protocol is different than the first communications protocol.

9. The method of claim 8, wherein:

the determining whether the first host device is accessing the target device includes determining whether the first host device is idle.

10. The method of claim 8, further comprising:

generating at least one response by the second host device responsive to receiving at least one request to access the target device.

11. The method of claim 8, further comprising:

determining whether any pending transactions involving the target device are complete before establishing communications between the second host device and the target device.

12. The method of claim 8, further comprising:

determining whether any pending transactions involving the target device are complete responsive to receiving a request to terminate access to the target device from the second host device.

13. The method of claim 12, further comprising:

enabling communications between the first host device and the target device responsive to determining that all pending transactions involving the target device are complete.

14. The method of clam 12, further comprising:

determining whether the first host device is accessing the target device; and

unblocking the second host device'"'"'s access to the target device when the first host device is not accessing the target device.

15. A computer readable memory comprising computer executable instructions, that when executed by a processor, perform a method comprising:

receiving a control signal from a first host device, the control signal requesting access to a target device;

determining whether the target device is being accessed by a second host device,

when the target device is not being accessed by the second host device;

generating a token responsive to the control signal, the token including a communication direction and an endpoint location associated with the target device;

examining the token to determine whether the token identifies a valid endpoint location and when the token identifies a valid endpoint, examining a status of the end point location;

writing the token to the endpoint location responsive to determining that the endpoint location is valid and the endpoint is not being accessed by the second host device; and

transferring data from the first host device to the endpoint location indicated by the token; and

when the target device is being accessed by the second host device, responding to the control signal received from the first host device with a stall response or a no acknowledge (NAK) response.

16. The computer readable memory of claim 15, wherein the token further includes a packet identifier field, an address field, and an endpoint address.

17. The computer readable memory of claim 15, wherein the generating a token comprises generating an IN token responsive to a request to transfer data from the target device to the first host device, and generating an OUT token responsive to a request to transfer data from the first host device to the target device.

18. The computer readable memory of claim 15, further comprising preventing the first host device from accessing the endpoint location responsive to the second host device accessing the endpoint location.