Method for designing structured ASICs in silicon processes with three unique masking steps

• US 7,895,559 B2
• Filed: 07/17/2008
• Issued: 02/22/2011
• Est. Priority Date: 06/09/2004
• Status: Active Grant

• Current Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Original Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Inventors: Bansal, Jai P.
• Primary Examiner(s): Levin, Naum B
• Application Number:
  US12/218,672
• Publication Number:
  US 20080282216A1
• Time in Patent Office: 950 Days
• Field of Search: 716/106, 716/116, 257/211, 326 40- 41, 438128-129
• US Class Current: 716/116
• CPC Class Codes: G06F 2115/06 Structured ASICs
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to a conventional standard cell library macro set. In addition to a core functional macro set, primary input/output buffers and commonly used single and dual port memory blocks are also defined in the library. The library includes all the ASIC synthesis, simulation, and physical design rules.

Claims

1. An application specific integrated circuit (ASIC) device comprising:

a core base cell comprising a plurality of semiconductor components interconnected by a first, second and third metal level having insulating layers therebetween;

a first metal level masked on said core base cell, said first metal level comprising a common mask to all ASIC devices for completing the ASIC device;

a second metal level masked through a common first via level mask through an insulating level deposited over said first metal level, said second metal level comprising a common mask;

a third metal level masked through a common second via level mask through an insulating level deposited over said second metal level, said third metal level comprising a first unique mask;

a third via level masked through an insulating level deposited over said third metal level, said third via level mask comprising a second unique mask; and

a fourth metal level masked on said third via level, said fourth level mask being a third unique mask to each of said semiconductor components for completing the ASIC device;

thereby completing the personalization of an ASIC device using only three unique masking levels.

2. The ASIC device of claim 1, wherein said third level comprises logic function personality and a wiring grid in an X-Y direction.

3. The ASIC device of claim 2, wherein said first common mask comprises inputs into said first level from said core base cell, and outputs from said first level to said second level.

4. The ASIC device of claim 3, wherein said second common mask comprises inputs into said second level from said first level, and outputs from said second level to said third level.

5. The ASIC device of claim 3, wherein said third unique mask and said wiring grid comprise inputs into said third level from said second level, and outputs from said third level to said fourth level.

6. The ASIC device of claim 3, further comprising VDD and GND pins in said first level, said VDD and said GND pins for biasing said inputs that are unused in said device into steady state, thereby preventing current from flowing through said unused inputs.

7. The ASIC device of claim 1, further comprising:

a microcircuit chip comprising a plurality of said core base cells formed thereon;

input and output buffers positioned along a periphery of said microcircuit chip; and

memory blocks positioned along said periphery of said microcircuit chip.

8. The ASIC gate device of claim 7, wherein said core base cells are configured to provide an inverter, said inverter comprising a driving strength of from 1×

to 6×

.

9. The ASIC device of claim 8, wherein said core base cells are configured to provide a multiplexer, an exclusive OR, or an exclusive NOR, said multiplexer, said exclusive OR, or said exclusive NOR comprising a driving strength of 1×

, 3×

, or 4×

.

10. The ASIC device of claim 7, wherein said core base cells are configured to provide a NAND gate, said NAND gate comprising driving strengths of 1×

, 2×

or 4×

.

11. The ASIC device of claim 7, wherein said core base cells are configured to provide a first input to said NAND gate, a second input to said NAND gate, and an output from said NAND gate, said first input to said NAND gate, said second input to said NAND gate, and said output from said NAND gate comprising driving strengths of 1×

, 2×

, or 4×

.

12. The ASIC device of claim 7, wherein said core base cells are configured to provide a DFF with asynchronous set/reset, said DFF comprising a driving strength of 1×

or 3×

.

13. The ASIC device of claim 7, wherein said core base cells are configured to provide a DFFS with scan and asynchronous reset, said DFFS comprising a driving strength of 1×

or 3×

.

14. The ASIC device of claim 1, wherein the semiconductor components comprise:

a first inverter, a second inverter, a third inverter and a fourth inverter;

a first two input NAND gate and a second two input NAND gate;

a three input NAND gate; and

a latch circuit.

15. The ASIC device of claim 14, wherein said first inverter, said second inverter, and said third inverter comprise a 1×

inverter;

said fourth inverter comprises a 3×

inverter;

said first NAND gate comprises a two input NAND gate;

said second NAND gate comprises a two input NAND gate; and

said third NAND gate comprises a three input NAND gate.