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Method for designing structured ASICs in silicon processes with three unique masking steps

  • US 7,895,559 B2
  • Filed: 07/17/2008
  • Issued: 02/22/2011
  • Est. Priority Date: 06/09/2004
  • Status: Active Grant
First Claim
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1. An application specific integrated circuit (ASIC) device comprising:

  • a core base cell comprising a plurality of semiconductor components interconnected by a first, second and third metal level having insulating layers therebetween;

    a first metal level masked on said core base cell, said first metal level comprising a common mask to all ASIC devices for completing the ASIC device;

    a second metal level masked through a common first via level mask through an insulating level deposited over said first metal level, said second metal level comprising a common mask;

    a third metal level masked through a common second via level mask through an insulating level deposited over said second metal level, said third metal level comprising a first unique mask;

    a third via level masked through an insulating level deposited over said third metal level, said third via level mask comprising a second unique mask; and

    a fourth metal level masked on said third via level, said fourth level mask being a third unique mask to each of said semiconductor components for completing the ASIC device;

    thereby completing the personalization of an ASIC device using only three unique masking levels.

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