Continuous flow instant logic binary circuitry actively structured by code-generated pass transistor interconnects

• US 7,895,560 B2
• Filed: 10/02/2006
• Issued: 02/22/2011
• Est. Priority Date: 10/02/2006
• Status: Expired due to Fees

• Current Assignee: WEND LLC
• Original Assignee: WEND LLC
• Inventors: Lovell, William Stuart
• Primary Examiner(s): Kik; Phallaka
• Application Number:
  US11/542,773
• Publication Number:
  US 20080082786A1
• Time in Patent Office: 1,604 Days
• Field of Search: 716/9, 716/10, 716/12, 716/13, 716/16, 708/130, 708/231
• US Class Current: 716/119
• CPC Class Codes: G06F 15/76 Architectures of general purpose stored program computers with program plugboard G06F15/08; multicomputers G06F15/16

Abstract

A processing space contains an array of operational transistors interconnected by circuit and signal pass transistors that when supplied with selected enable bits will structure a variety of circuits that will carry out any desired information processing. The Babbage/von Neumann Paradigm in which data are provided to circuitry that would operate on those data is reversed by structuring the desired circuits at the site(s) of the data, thereby to eliminate the von Neumann bottleneck and substantially increase the computing power of the device, with the apparatus conducting only non-stop Information Processing on a steady stream of data and code, with no repetitious Instruction and data transfers as in the normal computer being required. A code is defined that will identify the physical locations of every transistor in the processing space, which code will then enable only selected ones of the pass transistors therein so as to structure the circuits needed for any algorithm sought to be executed. The circuits so structured, operating independently of and in parallel with every other circuit so structured, are then restructured after each step into another group of circuits, so that almost no transistor will ever “sit idle,” but all of the processing space can be devoted entirely to information processing, thereby again to increase enormously the computing power of the device. The apparatus is also super-scalable, meaning that an Instant Logic Apparatus built around that processing space could be built to have any size, speed, and level of computer power desired.

Claims

1. Apparatus for information processing, comprising:

An array of passive energy transmitting devices, each having a number of terminals thereon that are connectible along directions as defined by a dimensionality of said array, each of said passive energy transmitting devices being capable of being transformed into a corresponding active energy transmitting device capable of receiving energy packets having information contained therein and performing information processing on said energy packets;

A first array of active energy transmitting devices having proximal and distal ends, said active energy transmitting devices being capable of passing energy packets therethrough upon an imposition thereto of an enabling signal, with said proximal ends of said active energy transmitting devices being connected respectively to different ones of said connectible terminals on said passive energy transmitting devices, and said distal ends of selected ones of said active energy transmitting devices being connected respectively to an energy source, an entry location for energy packets, and an energy sink;

A second array of active energy transmitting devices having proximal and distal ends, said active energy transmitting devices being capable of passing energy packets therethrough upon an imposition thereto of an enabling signal, with the proximal ends of each of said energy active transmitting devices of this second array that had not already been connected to an energy source, entry location for energy packets, or energy sink, connecting to each of said connectible terminals on each of said passive energy transmitting devices, with the distal ends of each of said active energy transmitting devices of this second array that had not already been connected to an energy source, entry location for energy packets, or energy sink, connecting to each of said connectible terminals of an adjacent passive energy transmitting device, in as many directions as may be defined by the dimensionality of said arrays of active and passive energy transmitting devices; and

Addressing means by which enabling signals can be directed to selected ones of said active energy transmitting devices;

whereupon

An imposition of an enabling signal onto one or more of said active energy transmitting devices connected to one or more of said passive energy transmitting devices will transform said one or more passive energy transmitting devices into corresponding active energy transmitting devices capable of performing information processing upon an entry of energy packets into said entry location for energy packets; and

Data entry means by which data bits (energy packets) requiring information processing are acquired and sent to appropriate ones of said data entry locations, so that upon a use of said data entry means by actual data entry, in conjunction with an entry of enabling bits to appropriate ones of said active energy transmitting devices as established by an algorithm being executed and the data provided, will bring about a desired information processing.

2. The apparatus of claim 1 wherein said apparatus, said passive energy transmitting devices and said active energy transmitting devices are all electronic circuits, said energy is electronic energy, and said enabling signal is an enabling voltage.

3. The apparatus of claim 2 wherein said electronic circuits for said passive energy transmitting circuits comprise operational transistors and said electronic circuits for active energy transmitting devices comprise pass transistors, said energy packets are electronic bits, and an array of operational transistors and pass transistors comprises a processing space.

4. The apparatus of claim 3 wherein an application of enabling voltages to said pass transistors is controlled by code entered into said processing space through a code selector unit.

5. The apparatus of claim 4 wherein said code selector comprises a circuit code selector and a signal code selector.

6. The apparatus of claim 5 wherein said circuit code selector comprises:

A number of circuit code input nodes each being connected respectively to a first input to an XNOR gate;

A number of XNOR gates being equal to the number of said circuit code input nodes;

Reference latches holding respective values “

0” and

“

1”

that connect respectively to a second input to each of said XNOR gates, whereupon an entry of the same bit value from said circuit code input node to said first input to said XNOR gate as a bit value of said reference latch that is connected to said second input to said XNOR gate will bring about a “

1”

bit output from said XNOR gate;

wherein

The said “

0” and

“

1”

bit values that are held in said reference latches are established in such a manner as to form a number of bit combinations of a pre-selected bit length, each of said bit combinations being distinct in terms of the bit values held from every other bit combination formed in that same manner;

Each of said distinct bit combinations is connected to said second inputs of a number of arrays of XNOR gates wherein a bit length of each said array of XNOR gates is the same as the bit lengths of said bit combinations;

Each XNOR gate of a particular said array of XNOR gates to which any one of said bit combinations is sent from said reference latches is a different XNOR gate from any XNOR gate to which a different one of said bit combinations has been sent;

A number of AND gates each having a number of inputs equal to the number of XNOR gates contained in each of said arrays of said XNOR gates, an output of each of said XNOR gates of a particular array of said XNOR gates being connected respectively to each of said inputs to that one of said AND gates to which are connected the outputs of those said XNOR gates that are connected to the particular AND gate, whereby

Upon all of the XNOR gates of a particular one of said arrays of said XNOR gates having yielded a “

1”

bit, said AND gate to which said particular one array of said XNOR gates connects will yield a “

1”

bit;

An array of enable latches equal in number to the number of said AND gates, to which gates of said enable latches are respectively connected outputs of said AND gates, and

An array of voltage sources equal in number to the number of said enable latches and being connected respectively to each of said enable latches, whereby

A receipt of a “

1”

bit by a particular one of said enable latches from the said AND gate connected thereto will cause a voltage from that particular said voltage source that is connected to said particular one of said enable latches to pass through said particular one of said enable latches, with said voltage then serving as a “

1”

bit to enable that pass transistor within a processing space to which an enable latch is connected, as one part of structuring a circuit using operational transistors of said processing space as one part of structuring a circuit using the operational transistors of said processing space.

7. The apparatus of claim 5 wherein said signal code selector comprises:

A first DMUX having lines therefrom connecting to three second DMUXs, pertaining respectively to drain, gate, and source terminals of an operating transistor serving as an originating transistor, with a pass transistor to be enabled being connected to that one of said drain, gate, and source terminals of said originating transistor that had been selected by said first DMUX;

An array of second DMUXs, each of which connects to one of said lines connecting from said first DMUX, and has two lines connecting thereto that pertain to upward and rightward directions from said originating transistor, with said pass transistor that is to be enabled being directed in a direction as defined by that same said second DMUX that had itself been selected by said first DMUX; and

An array of six third DMUXs, each of which connects to one of said two lines connecting from one of said three second DMUXs, and has three lines connected therefrom that pertain respectively to the drain, gate, and source terminals of an operating transistor acting as a receiving transistor;

An array of six 3-line code enablers, with each of said code enablers being connected to one of said three lines connecting from one of said six third DMUXs and having enabling lines connecting therefrom, with each of said lines being connected to the gate terminal of a pass transistor; and

One or more voltage sources that collectively will connect to each of said code enablers, whereby a “

1”

bit received by one of said code selectors through said first, second and third DMUXs will direct voltage from said voltage sources to the gate terminal of that pass transistor that is connected to that terminal of said receiving transistor as had been selected by said first, second, and third DMUXs.

8. The apparatus of claim 4 wherein said processing space has a manifold-like construction, comprising:

A multiplicity of manifold lines having first ends that connect indirectly to at least one operational transistor that is physically located on an outer surface of said processing space, along an edge of said processing space, or at a corner of said processing space, and second ends that connect directly to respective operational transistors that are physically located at opposite positions with respect to a location of each said at least one operational transistor, within an opposite surface, an opposite edge, or an opposite corner, respectively;

A multiplicity of manifold line pass transistors having a number that is equal to the number of said manifold lines, connected respectively to said first ends of said manifold lines that connect indirectly to said at least one operational transistor, and further connected to at least one terminal of said at least one operational transistor, thereby making direct connection thereto;

A multiplicity of manifold line pass transistor enablers having a number that is equal to the number of said manifold line pass transistors that are connected respectively to each of said manifold line pass transistors, whereby

An enabling voltage from one of said manifold line pass transistor enablers to that manifold line pass transistor to which connected will cause said manifold line pass transistor to become conductive, thereby

Enabling a signal voltage to be conveyed from a terminal of a first operational transistor to a second operational transistor that is physically located oppositely to said first operational transistor, said first and second operational transistors being located on opposite sides, opposite edges, or opposite corners of said processing space.