Method of manufacturing semiconductor component with gate and shield electrodes in trenches

• US 7,897,462 B2
• Filed: 11/14/2008
• Issued: 03/01/2011
• Est. Priority Date: 11/14/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Barber, Duane B., Pratt, Brian, Burke, Peter A.
• Primary Examiner(s): Sandvik; Benjamin P
• Assistant Examiner(s): Kuo; W. Wendy
• Application Number:
  US12/271,083
• Publication Number:
  US 20100123192A1
• Time in Patent Office: 837 Days
• Field of Search: 438/270, 438/283, 438/294, 438/589, 438/696, 438/702, 257/E21.177, 257/E21.41, 257/E21.419, 257/E21.46
• US Class Current: 438/270
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

Claims

1. A method for manufacturing a semiconductor component, comprising:

providing a semiconductor material having first and second major surfaces;

forming a plurality of trenches in the semiconductor material;

forming a first layer of dielectric material over the plurality of trenches;

forming a first electrode in a first portion of a first trench of the plurality of trenches, the first electrode having opposing sides and the first trench having at least one sidewall;

thinning the first layer of dielectric material;

recessing the first electrode in the first portion of the first trench of the plurality of trenches after thinning the first layer of dielectric material;

further thinning the first layer of dielectric material to expose portions of the opposing sides of the first electrode after recessing the first electrode;

forming a second layer of dielectric material over at least the first trench of the plurality of trenches; and

forming a second electrode in a second portion of the first trench.

2. The method of claim 1, wherein thinning the first layer of dielectric material exposes the portions of the opposing sides of the first electrode in the first portion of the first trench of the plurality of trenches.

3. The method of claim 1, further including forming a first doped region adjacent the first major surface and the first trench of the plurality of trenches.

4. The method of claim 3, further including forming a second doped region within the first doped region.

5. The method of claim 1, further including:

forming a third electrode in a first portion of a second trench of the plurality of trenches, wherein the third electrode has opposing sides, the second trench has at least one sidewall, and wherein forming the first layer of dielectric material includes forming the first layer of dielectric material in the second trench;

thinning the first layer of dielectric material in the second trench;

recessing the third electrode in the first portion of the second trench;

further thinning the first layer of dielectric material in the second trench to expose portions of opposing sides of the third electrode;

forming a portion of the second layer of dielectric material over the second trench; and

forming a fourth electrode in a second portion of the second trench.

6. The method of claim 1, further including:

forming a third electrode in a third trench of the plurality of trenches; and

recessing the third electrode.

7. The method of claim 1, further including forming an electrical contact to the semiconductor material.

8. The method of claim 7, wherein forming the electrical contact includes forming a top side electrical contact.

9. The method of claim 1, further including forming a silicide from the second electrode.

10. The method of claim 9, wherein the silicide is cobalt silicide.

12. The method of claim 1, wherein further thinning the first layer of dielectric material creates a dielectric stub laterally adjacent the first electrode.

13. The method of claim 1, wherein the dielectric stub is an oxide stub.

11. A method for manufacturing a semiconductor component, comprising:

providing a semiconductor material having first and second major surfaces;

forming a plurality of trenches in the semiconductor material;

forming a first layer of dielectric material over the plurality of trenches;

forming a first electrode in a first portion of a first trench of the plurality of trenches, the first electrode having opposing sides and the first trench having at least one sidewall;

thinning the first layer of dielectric material;

recessing the first electrode in the first portion of the first trench of the plurality of trenches;

further thinning the first layer of dielectric material to expose portions of the opposing sides of the first electrode;

forming a second layer of dielectric material over at least the first trench of the plurality of trenches;

removing the second layer of dielectric'"'"'material from a portion of the at least one sidewall of the first trench, wherein further thinning the first layer of dielectric material and removing the second layer of dielectric material from the portion of the at least one sidewall forms a dielectric stub;

forming a third layer of dielectric material on the at least one sidewall of the first trench; and

forming the first electrode on the third layer of dielectric material; and

forming a second electrode in a second portion of the first trench.

14. The method of claim 11, further including:

forming a third electrode in a first portion of a second trench of the plurality of trenches, wherein the third electrode has opposing sides, the second trench has at least one sidewall, and wherein forming the first layer of dielectric material includes forming the first layer of dielectric material in the second trench;

thinning the first layer of dielectric material in the second trench;

recessing the third electrode in the first portion of the second trench;

further thinning the first layer of dielectric material in the second trench to expose portions of opposing sides of the third electrode;

forming a portion of the second layer of dielectric material over the second trench; and

forming a fourth electrode in a second portion of the second trench.

15. The method of claim 11, wherein further thinning the first layer of dielectric material creates a dielectric stub laterally adjacent the first electrode.