Semiconductor device and a method of manufacturing the same

• US 7,898,032 B2
• Filed: 02/07/2007
• Issued: 03/01/2011
• Est. Priority Date: 03/23/2006
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Suzuki, Takaya, Ipposhi, Takashi
• Primary Examiner(s): PRENTY, MARK V
• Application Number:
  US11/672,487
• Publication Number:
  US 20070221995A1
• Time in Patent Office: 1,483 Days
• Field of Search: 257/350, 257/379, 257/536, 257/538
• US Class Current: 257/350
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention realizes the miniaturization of a semiconductor device. On a first insulation film, an island-like semiconductor layer and a second insulation film which surrounds the semiconductor layer are formed, and resistance elements (for example, poly-silicon resistance elements) which are formed of a conductive film are arranged to be overlapped to an upper surface of the semiconductor layer in plane.

Claims

1. A semiconductor device comprising:

a first insulation film formed over a semiconductor base body;

an island-like semiconductor layer which is formed over the first insulation film;

a second insulation film which is formed over the first insulation film so that the second insulation film is embedded into a gap formed by patterning the semiconductor layer and is connected to the first insulation film; and

a resistance element which is formed over the semiconductor layer in a state that the resistance element is overlapped to an upper surface of the semiconductor layer in plane,

wherein the semiconductor layer has a planar size smaller than a planar size of the resistance element,

wherein the resistance element is arranged in a state that the resistance element covers the whole semiconductor layer, and

wherein the semiconductor layer is formed as a dummy pattern and is in a floating state.

3. A semiconductor device according to claim 1,

wherein the upper surface of the semiconductor layer is covered with a third insulation film which has a height lower than the upper surface of the second insulation film, and

wherein the resistance element is insulated electrically from the semiconductor layer by the third insulation film.

4. A semiconductor device according to claim 1,

wherein the resistance element is formed of a silicon film.

5. A semiconductor device according to claim 1,

wherein the resistance element includes a silicon film and silicide layers which are formed over both end portions of the upper surface of the silicon film, and

wherein the silicide layers are arranged over the second insulation film.

6. A semiconductor device according to claim 1,

wherein the resistance element includes a silicon film and silicide layers which are formed over the both end portions of the upper surface of the silicon film, and

wherein the silicide layers are arranged to extend over the second insulation film and the semiconductor layer.

28. A semiconductor device according to claim 1, further comprising:

a fourth insulation film and first silicide layers,

wherein the fourth insulation film is formed over the resistance element selectively, and

wherein the first silicide layers are formed over the surface of the resistance element so as to be aligned with the fourth insulation film.

2. A semiconductor device comprising:

a semiconductor base body;

a first insulation film formed over the semiconductor base body;

a semiconductor layer formed over the first insulation film;

a second insulation film formed over the first insulation film;

a third insulation film formed over the semiconductor layer; and

a resistance element which is arranged over the third insulation film,

wherein the second insulation film is embedded into a gap formed by patterning the semiconductor layer so as to divide the semiconductor layer into a plurality of island-like semiconductor layers and is connected to the first insulation film,

wherein the resistance element is overlapped to an upper surface of one of the plurality of island-like semiconductor layers in plane and is insulated electrically from one of the plurality of island-like semiconductor layers by the third insulation film,

wherein the resistance element is arranged to be in a state that the resistance element covers the whole semiconductor layer, and

wherein the semiconductor layer is formed as a dummy pattern and is in a floating state.

23. A semiconductor device according to claim 2,

wherein the resistance element includes a silicon film and silicide layers which are formed over both end portions of the upper surface of the silicon film, and

wherein the silicide layers are arranged over the second insulation films.

24. A semiconductor device according to claim 2,

wherein the resistance element includes a silicon film and silicide layers which are formed over both end portions of the upper surface of the silicon film, and

wherein the silicide layers are arranged to extend over the second insulation film and one of the plurality of island-like semiconductor layers.

27. A semiconductor device according to claim 2,

wherein the resistance element is formed of a silicon film.

7. A semiconductor device comprising:

a semiconductor base body;

a first insulation film formed over the semiconductor base body;

a semiconductor layer formed over the first insulation film;

a second insulation film formed over the first insulation film;

a third insulation film formed over the semiconductor layer; and

a resistance element which is arranged over the third insulation film,

wherein the second insulation film is embedded into a gap formed by patterning the semiconductor layer so as to divide the semiconductor layer into a plurality of island-like semiconductor layers and is connected to the first insulation film,

wherein the resistance element is overlapped to upper surfaces of the plurality of island-like semiconductor layers in plane and is insulated electrically from the plurality of island-like semiconductor layers by the third insulation film, and

wherein each of the island-like semiconductor layers is formed as a dummy pattern and is in a respective floating state.

8. A semiconductor device comprising:

a semiconductor base body;

a first insulation film formed over the semiconductor base body;

a semiconductor layer formed over the first insulation film;

a second insulation film formed over the first insulation film;

a third insulation film formed over the semiconductor layer; and

a resistance element which is arranged over the third insulation film,

wherein the second insulation film is embedded into a gap formed by patterning the semiconductor layer so as to divide the semiconductor layer into a plurality of island-like semiconductor layers and is connected to the first insulation film, and

wherein the plurality of island-like semiconductor layers includes a plurality of first semiconductor layers and, a plurality of second semiconductor layers,

wherein the resistance element is overlapped to upper surfaces of the plurality of first semiconductor layers in plane, arranged so as to be surrounded by the plurality of second semiconductor layers, and is insulated electrically from the plurality of first semiconductor layers by the third insulation film, and

wherein the plurality of first semiconductor layers and the plurality of second semiconductor layers are formed as a dummy patterns and are in respective floating states.

9. A semiconductor device comprising:

a semiconductor base body;

a first insulation film formed over the semiconductor base body;

a semiconductor layer formed over the first insulation film;

a second insulation film formed over the first insulation film which is embedded into a gap formed by patterning the semiconductor layer so as to divide the semiconductor layer into a plurality of first semiconductor layers and a plurality of second semiconductor layers, and said second insulation film connected to the first insulation film;

a third insulation film formed over one of the plurality of second semiconductor layers;

a resistance element which is overlapped to an upper surface of one of the plurality of second semiconductor layers in plane and is insulated electrically from the one of the plurality of second semiconductor layers by the third insulation film; and

a transistor element which has a first source and a first drain formed in one of the plurality of first semiconductor layers, a first gate insulation film formed over one of the plurality of first semiconductor layers, and a first gate formed over the gate insulation film,

wherein the first gate insulation film is composed of the same film as the third insulation film,

wherein the first gate is composed of the same film as the resistance element, and

wherein the second semiconductor layer is formed as a dummy pattern and is in a floating state.

10. A semiconductor device according to claim 9,

wherein the resistance element is arranged in a state that the resistance element is overlapped to a portion of or the whole of one of plurality of second semiconductor layers in plane.

11. A semiconductor device according to claim 9,

wherein one of the plurality of second semiconductor layers has a planar size smaller than a planar size of the resistance element, and

wherein the resistance element is arranged in a state that the resistance element covers the whole of one of the plurality of second semiconductor layers.

12. A semiconductor device according to claim 9,

wherein one of the plurality of second semiconductor layers has a planar size larger than a planar size of the resistance element, and

wherein the resistance element is arranged in a state that the whole resistance element is positioned over one of the plurality of second semiconductor layers.

13. A semiconductor device according to claim 9,

wherein the resistance element is formed in a rectangular planar shape, having long sides and short sides,

wherein the plurality of first semiconductor layers and the plurality of second semiconductor layers are formed in a rectangular planar shape having long sides shorter than long sides of the resistance element and short sides longer than short sides of the resistance element, and

wherein the resistance element is arranged in a state that the short sides of the resistance element are positioned inside the short sides of the semiconductor layer and the long sides of the resistance element are positioned outside the long sides of the semiconductor layer.

14. A semiconductor device according to claim 9,

wherein the upper surface of one of the plurality of second semiconductor layers is covered with a third insulation film which has a height lower than the upper surface of the second insulation film, and

wherein the resistance element is insulated electrically from one of the plurality of second semiconductor layers by the third insulation film.

15. A semiconductor device according to claim 9,

wherein the resistance element is formed of a silicon film.

16. A semiconductor device according to claim 9,

wherein the transistor element is constituted of a MISFET.

17. A semiconductor device according to claim 13,

wherein the resistance element includes a silicon film and silicide layers which are formed over both end portions of the upper surface of the silicon film, and

wherein the silicide layers are arranged over the second insulation films.

18. A semiconductor device according to claim 13,

wherein the resistance element includes a silicon film and silicide layers which are formed over the both end portions of the upper surface of the silicon film, and

wherein the silicide layers are arranged to extend over the second insulation film and one of the plurality of second semiconductor layers.

29. A semiconductor device according to claim 9,

wherein the transistor element includes a low breakdown voltage transistor and a high breakdown voltage transistor,

wherein a thickness of the high breakdown voltage transistor is larger than a thickness of the low breakdown voltage transistor, and

wherein the third insulation film is the gate insulation film of the high breakdown voltage transistor.

30. A semiconductor device according to claim 9, further comprising:

a fourth insulation film and a plurality of silicide layers,

wherein the silicide layers are formed over a surface of the resistance element, the first source, and the first gate,

wherein the fourth insulation film is formed over the resistance element selectively, and

wherein the silicide layers formed over the surface of the resistance element are arranged to be aligned with the fourth insulation film.

19. A semiconductor device comprising:

a semiconductor base body;

a first insulation film formed over the semiconductor base body;

a semiconductor layer formed over the first insulation film;

a second insulation film formed over the first insulation film which is embedded into a gap formed by patterning the semiconductor layer so as to divide the semiconductor layer into a plurality of first semiconductor layers and a plurality of second semiconductor layers, and said second insulation film connected to the first insulation film;

a third insulation film formed over one of the plurality of second semiconductor layers;

a resistance element which is overlapped to an upper surface of the plurality of second semiconductor layers in plane and is insulated electrically from the one of the plurality of second semiconductor layers by the third insulation film; and

a transistor element which has a first source and a first drain formed in one of the plurality of first semiconductor layers, a first gate insulation film formed over one of the plurality of first semiconductor layers, and a first gate formed over the gate insulation film,

wherein the first gate insulation film is composed of the same film as the third insulation film,

wherein the first gate is composed of the same film as the resistance element, and

wherein the plurality of second semiconductor layers are formed as a dummy pattern and are in respective floating states.

22. A semiconductor device according to claim 19,

wherein the transistor element is constituted of a MISFET.

31. A semiconductor device according to claim 19, further comprising:

a fourth insulation film and a plurality of silicide layers,

wherein the silicide layers are formed over a surface of the resistance element, the first source, and the first gate,

wherein the fourth insulation film is formed over the resistance element selectively, and

wherein the silicide layers formed over the surface of the resistance element are arranged to be aligned with the fourth insulation film.

20. A semiconductor device comprising:

a semiconductor base body;

a first insulation film formed over the semiconductor base body;

a semiconductor layer formed over the first insulation film;

a second insulation film formed over the first insulation film which is embedded into a gap formed by patterning the semiconductor layer so as to divide the semiconductor layer into a plurality of first semiconductor layers, a plurality of second semiconductor layers, and a plurality of third semiconductor layers, and said second insulation film is connected to the first insulation film;

a third insulation film formed over one of the plurality of second semiconductor layers;

a resistance element which is overlapped to an upper surface of the plurality of second semiconductor layers in plane, arranged so as to be surrounded by the plurality of third semiconductor layers, and is insulated electrically from the one of the plurality of second semiconductor layers by the third insulation film; and

a transistor element which has a first source and a first drain formed in one of the plurality of first semiconductor layers, a first gate insulation film formed over one of the plurality of first semiconductor layers, and a first gate formed over the gate insulation film,

wherein the first gate insulation film is composed of the same film as the third insulation film,

wherein the first gate is composed of the same film as the resistance element, and

wherein the plurality of second semiconductor layers and the plurality of third semiconductor layers are formed as a dummy patterns and are in respective floating states.

25. A semiconductor device according to claim 20,

wherein the transistor element is constituted of a MISFET.

32. A semiconductor device according to claim 20, further comprising:

a fourth insulation film and a plurality of silicide layers,

wherein the silicide layers are formed over a surface of the resistance element, the first source, and the first gate,

wherein the fourth insulation film is formed over the resistance element selectively, and

wherein the silicide layers formed over the surface of the resistance element are arranged to be aligned with the fourth insulation film.

21. A semiconductor device comprising:

a semiconductor base body;

a first insulation film formed over the semiconductor base body;

a semiconductor layer formed over the first insulation film;

a second insulation film formed over the first insulation film which is embedded into a gap formed by patterning the semiconductor layer so as to divide the semiconductor layer into a plurality of first semiconductor layers and a plurality of second semiconductor layers, and is connected to the first insulation film;

a third insulation film formed over one of the plurality of second semiconductor layers;

a resistance element which is overlapped to an upper surface of one of the plurality of second semiconductor layers in plane and is insulated electrically from the one of the plurality of second semiconductor layers by the third insulation film; and

a transistor element which has a first source and a first drain formed in one of the plurality of first semiconductor layers, a first gate insulation film formed over one of the plurality of first semiconductor layers, and a first gate formed over the gate insulation film,

wherein the first gate insulation film is composed of the same film as the third insulation film,

wherein the first gate is composed of the same film as the resistance element, and

wherein a wiring for fixing a potential of one of the plurality of second semiconductor layers is coupled to one of the plurality of second semiconductor layers.

26. A semiconductor device according to claim 21,

wherein the transistor element is constituted of a MISFET.

33. A semiconductor device according to claim 21, further comprising:

a fourth insulation film and a plurality of silicide layers,

wherein the silicide layers are formed over a surface of the resistance element, the first source, and the first gate,

wherein the fourth insulation film is formed over the resistance element selectively, and

wherein the silicide layers formed over the surface of the resistance element are arranged to be aligned with the fourth insulation film.

34. A semiconductor device comprising:

a first insulation film formed over a semiconductor base body;

an island-like semiconductor layer which is formed over the first insulation film;

a second insulation film which is formed over the first insulation film so that the second insulation film is embedded into a gap formed by patterning the semiconductor layer and is connected to the first insulation film; and

a resistance element which is formed over the semiconductor layer in a state that the resistance element is overlapped to an upper surface of the semiconductor layer in plane,

wherein the resistance element is formed in a rectangular planar shape having long sides and short sides,

wherein the semiconductor layer is formed in a rectangular planar shape having long sides shorter than long sides of the resistance element and short sides longer than short sides of the resistance element,

wherein the resistance element is arranged in a state that the short sides of the resistance element are positioned outside the short sides of the semiconductor layer and the long sides of the resistance element are positioned inside the long sides of the semiconductor layer, and

wherein the semiconductor layer is formed as a dummy pattern and is in a floating state.

35. A semiconductor device according to claim 34,

wherein the upper surface of the semiconductor layer is covered with a third insulation film which has a height lower than the upper surface of the second insulation film, and

wherein the resistance element is insulated electrically from one of the semiconductor layers by the third insulation film.

36. A semiconductor device according to claim 34,

wherein the resistance element is formed of a silicon film.

37. A semiconductor device according to claim 34,

wherein the resistance element includes a silicon film and silicide layers which are formed over both end portions of the upper surface of the silicon film, and

wherein the silicide layers are arranged over the second insulation film.

38. A semiconductor device according to claim 34,

wherein the resistance element includes a silicon film and silicide layers which are formed over the both end portions of the upper surface of the silicon film, and

wherein the silicide layers are arranged to extend over the second insulation film and the semiconductor layer.

39. A semiconductor device according to claim 34, further comprising:

a fourth insulation film and first silicide layers,

wherein the fourth insulation film is formed over the resistance element selectively, and

wherein the first silicide layers are formed over the surface of the resistance element so as to be aligned with the fourth insulation film.