Block contact architectures for nanoscale channel transistors

• US 7,898,041 B2
• Filed: 09/14/2007
• Issued: 03/01/2011
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Doczy, Mark L., Shah, Uday, Chau, Robert S., Radosavljevic, Marko, Kavalieros, Jack, Doyle, Brian S., Brask, Justin K., Majumdar, Amlan, Datta, Suman
• Primary Examiner(s): Andújar; Leonardo
• Assistant Examiner(s): HARRISTON, WILLIAM A
• Application Number:
  US11/855,823
• Publication Number:
  US 20080258207A1
• Time in Patent Office: 1,264 Days
• Field of Search: 257/368, 257/401
• US Class Current: 257/401
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

Claims

1. An apparatus comprising:

a plurality of parallel semiconductor bodies, each of the plurality having a top surface and a pair of laterally opposite sidewalls, each of said plurality having a channel region between a source region and a drain region;

a single gate electrode formed adjacent to and over said channel region of each of said plurality of bodies;

a first source contact to a source region of at least a first of the plurality of parallel semiconductor bodies;

a second source contact to a source region of at least a second, of the plurality of parallel semiconductor bodies, wherein the second source contact does not contact the first of the plurality of parallel semiconductor bodies and the first source contact does not contact the second of the plurality of parallel semiconductor bodies; and

a single drain contact to a drain region of at least both the first and second of the plurality of parallel semiconductor bodies, wherein the drain contact is of a same metallization level as the first and second source contacts.

2. The apparatus of claim 1, wherein said parallel bodies have a first width and a first pitch, wherein said first pitch is less than a pitch which can be defined by a photolithography process.

3. The apparatus of claim 2, wherein said photolithography process uses 193 nanometer lithography.

4. The apparatus of claim 2, wherein said first pitch is less than 110 nanometers.

5. The apparatus of claim 2, wherein said pitch is one half of said pitch which can be defined by said photolithography process.

6. The apparatus of claim 1, further comprising a single drain landing pad in direct contact with all of said drain regions of said plurality of parallel bodies, wherein said drain landing pad is of the same material as said plurality of parallel bodies and wherein said drain contact is in direct contact with said drain landing pad.

7. The apparatus of claim 1, wherein said plurality of parallel bodies formed from a material selected from the group consisting of silicon, germanium, silicon germanium, GaAs, InSb and carbon nanotubes.

8. The apparatus of claim 7, wherein said plurality of parallel bodies are formed on an insulating substrate.

9. The apparatus of claim 1, wherein at least one of the source contact or drain contact has a length that is substantially smaller than a width.

10. The apparatus of claim 1, wherein the drain contact further contacts a sidewall of the drain region of a semiconductor body having a source region not electrically coupled to either the first source contact or second source contact.

11. The apparatus of claim 1, wherein said parallel bodies have a first width and a first pitch, wherein said first pitch is less than the width of the drain contact.

12. The apparatus of claim 1, wherein said plurality of parallel bodies formed from a material selected from the group consisting of silicon, germanium, silicon germanium, GaAs, InSb and carbon nanotubes.

13. An apparatus comprising:

a plurality of parallel semiconductor bodies, each of the plurality having a top surface and a pair of laterally opposite sidewalls, each of said plurality having a channel region between a source region and a drain region;

a single gate electrode formed adjacent to and over said channel region of each of said plurality of bodies;

a first drain contact to a drain region of at least a first of the plurality of parallel semiconductor bodies;

a second drain contact to a drain region of at least a second of the plurality of parallel semiconductor bodies, wherein the second drain contact does not contact the first of the plurality of parallel semiconductor bodies and the first drain contact does not contact the second of the plurality of parallel semiconductor bodies; and

a single source contact to a source region of at least both the first and second of the plurality of parallel semiconductor bodies, wherein the source contact is of a same metallization level as the first and second drain contacts.

14. The apparatus of claim 13, further comprising a single source landing pad in direct contact with all of said source regions of said plurality of parallel bodies, wherein said source landing pad is of the same material as said parallel bodies and wherein said source contact is in direct contact with said source landing pad.

15. The apparatus of claim 13, wherein at least one of the source contact or drain contact has a length that is substantially smaller than a width.

16. The apparatus of claim 13, wherein the source contact further contacts a sidewall of the source region of a semiconductor body having a drain region not electrically coupled to either the first drain contact or second drain contact.

17. The apparatus of claim 13, wherein said parallel bodies have a first width and a first pitch, wherein said first pitch is less than the width of the source contact.

18. The apparatus of claim 13, wherein said plurality of parallel bodies formed from a material selected from the group consisting of silicon, germanium, silicon germanium, GaAs, InSb and carbon nanotubes.

19. An apparatus comprising:

a plurality of parallel semiconductor bodies, each of the plurality having a top surface and a pair of laterally opposite sidewalls, each of said plurality having a channel region between a source region and a drain region;

a single gate electrode formed adjacent to and over said channel region of each of said plurality of bodies;

a first source contact to a source region of at least a first of the plurality of parallel semiconductor bodies;

a second source contact to a source region of at least a second, different than the first, of the plurality of parallel semiconductor bodies; and

a single drain contact to a drain region of at least both the first and second of the plurality of parallel semiconductor bodies, wherein the single drain contact further contacts a sidewall of a drain region of at least a third of the plurality of parallel semiconductor bodies having a source region not electrically coupled to any source contact.

20. An apparatus comprising:

a plurality of parallel semiconductor bodies, each of the plurality having a top surface and a pair of laterally opposite sidewalls, each of said plurality having a channel region between a source region and a drain region;

a single gate electrode formed adjacent to and over said channel region of each of said plurality of bodies;

a first drain contact to a drain region of at least a first of the plurality of parallel semiconductor bodies;

a second drain contact to a drain region of at least a second, different than the first, of the plurality of parallel semiconductor bodies; and

a single source contact to a source region of at least both the first and second of the plurality of parallel semiconductor bodies, wherein the single source contact further contacts a sidewall of a source region of at least a third of the plurality of parallel semiconductor bodies having a drain region not electrically coupled to any drain contact.