Radio frequency power semiconductor device package comprising dielectric platform and shielding plate

• US 7,898,057 B2
• Filed: 03/23/2006
• Issued: 03/01/2011
• Est. Priority Date: 01/10/2004
• Status: Expired due to Fees

• Current Assignee: Estivation Properties LLC (Intellectual Ventures LLC)
• Original Assignee: HVVi Semiconductors Incorporated
• Inventors: Davies, Robert Bruce, Seely, Warren Leroy, Pavio, Jeanne S
• Primary Examiner(s): Gurley, Lynne A
• Assistant Examiner(s): ARENA, ANDREW OWENS
• Application Number:
  US11/387,617
• Publication Number:
  US 20070090434A1
• Time in Patent Office: 1,804 Days
• Field of Search: 257/666, 257/675, 257/676, 257/690, 257/712, 257/713, 257/499, 257/500, 257/501, 257/502, 257/503, 257/506, 257/522, 257/618, 257/619, 257/622, 257/E29.11, 257/E29.112, 257/E29.116, 257/E29.118, 257/E29.12, 257/E29.122, 257/E29.123, 257/E29.126, 257/E29.127, 257/E29.128, 257/E29.13, 257/E29.131, 257/E29.134, 257/E29.226, 257/E29.229, 257/E29.242, 257/E29.255, 257/E29.256, 257/E29.257, 257/E29.262, 257/E29.263, 257/E29.268, 257/E23.01, 257/E23.011, 257/E23.031, 257/E23.151, 257/E23.153, 257/E23.168
• US Class Current: 257/522
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/83193 wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 23/047 the other leads being parallel to the base
• CPC Class Codes: H01L 23/051 another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
• CPC Class Codes: H01L 23/10 : characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/4824 : Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/49844 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0296 : involving a specific disposition of the protective devices
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 29/0661 : specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 : of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 : Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 : Field plates
• CPC Class Codes: H01L 29/41741 : for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42372 : characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 : characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/66681 : Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66712 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66719 : With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 : with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7817 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

Claims

1. A radio frequency (RF) semiconductor device comprising:

a die including an active area comprising an array of transistor cells, one or more of the transistor cells having a source region, a gate electrode and a drain region;

the drain regions of one or more of the transistor cells being coupled together, a metal gate interconnection on an upper surface of the die and coupled to the gate electrodes of the cells, a metal source interconnection on the upper surface of the die and coupled to the source regions of the cells, and a metal drain interconnection on a bottom surface of the die and coupled to the drain regions of the cells; and

a package to make electrical connections to the source regions, gate electrodes and drain regions of the cells, said package including an external source lead serving as a heat sink and coupled to the source interconnection, an external gate lead coupled to the gate interconnection, and an external drain lead coupled to the drain interconnection;

wherein the die further comprises a dielectric platform surrounding the active area and wherein the gate interconnection is over the dielectric platform to at least partially shield the gate electrode from the drain region of the die, and further comprising a shielding plate being coupled to the external source lead of the package via the source region and being disposed between the gate interconnection and the drain region to at least partially decouple the capacitance between the gate electrode and the drain region; and

wherein said dielectric platform comprises a matrix of silicon dioxide vertical structures and wherein the vertical structures are separated by cavities, top portions of the cavities are plugged and lower portions of the cavities are filled essentially with air.

2. The device of claim 1 wherein the source lead, gate lead and drain lead are coupled to a printed circuit board in a transmitter for a cellular base transceiver station.

3. The device of claim 1 wherein the source interconnection comprises:

a generally planar source metallization layer overlying the active area; and

metal posts coupled at their lower ends to the source regions of the cells, upper portions of the posts being coupled to the metallization layer.

4. The device of claim 1 wherein the die includes an epitaxial layer in which the active area is located, the die further including a heavily doped region beneath the epitaxial layer, and wherein the dielectric platform extends through the epitaxial layer into the heavily doped region to provide edge termination for the outer boundary of the active area to induce planar breakdown in the device.

5. The device of claim 1 wherein said dielectric platform is greater than 10 microns wide and 4 microns deep.

6. The device of claim 1 wherein the dielectric platform occupies greater than 10 percent of the total die area.

7. A semiconductor package comprising:

a semiconductor die;

a first lead;

a pedestal extending from a first surface of the first lead; and

a non-conductive member adjacent the pedestal, wherein a first portion of the semiconductor die is coupled to a first portion of the pedestal and a second portion of the semiconductor die is coupled to a first portion of the non-conductive member;

wherein the semiconductor die further comprises a dielectric platform surrounding an active area and wherein a gate interconnection is over the dielectric platform to at least partially shield a gate electrode from a drain region of the semiconductor die, and further comprising a shielding plate being coupled to an external source lead of the semiconductor package via a source region of the semiconductor die and being disposed between the gate interconnection and the drain region to at least partially decouple the capacitance between the gate electrode and the drain region; and

wherein said dielectric platform comprises a matrix of silicon dioxide vertical structures and wherein the vertical structures are separated by cavities, top portions of the cavities are plugged and lower portions of the cavities are filled essentially with air.

8. The semiconductor package of claim 7 further comprising:

the active area in the semiconductor die having a plurality of transistor cells, one or more of the cells having a gate electrode, a drain region and a source region;

a conductive source interconnect on a upper surface of the semiconductor die and over the active area;

a conductive gate interconnect on the upper surface of the semiconductor die and surrounding the source interconnect, and a conductive drain interconnect on a lower surface of the semiconductor die;

wherein the pedestal is connected to the source interconnect.

9. The semiconductor package of claim 8 wherein the non-conductive member surrounds the pedestal and has a conductor on a surface thereof, inner portions of the conductor being connected to the gate interconnect, and wherein the semiconductor package further comprises:

a second lead connected to outer portions of the conductor; and

a third lead connected to the drain interconnect.

10. The semiconductor package of claim 9 wherein said semiconductor die and leads are constructed so that the device operates at frequencies of greater than about 500 MHz and dissipates more than about 5 watts of power.

11. The semiconductor package of claim 7, wherein the die is mounted to the pedestal such that the periphery of the die extends from the pedestal and overlies a portion of the non-conductive member.

12. A radio frequency (RF) power transistor package for housing a RF power transistor die having a first electrode interconnection and a control electrode interconnection on a first major surface of the die and a second electrode interconnection on a second major surface of the die, the RF power transistor package comprising:

a first isolation ring having a first major surface and a second major surface; and

a first lead coupled to said first major surface of said first isolation ring, said first lead having a die mount pedestal adjacent to said first isolation ring wherein a surface of said die mount pedestal is planar to or above said second major surface of said first isolation ring;

wherein the die comprises a dielectric platform surrounding the active area and wherein a gate interconnection is over the dielectric platform to at least partially shield a gate electrode from a drain region of the die, and further comprising a shielding plate being coupled to an external source lead of the transistor package via a source region of the transistor die and being disposed between the gate interconnection and the drain region to at least partially decouple the capacitance between the gate electrode and the drain region; and

wherein said dielectric platform comprises a matrix of silicon dioxide vertical structures and wherein the vertical structures are separated by cavities, top portions of the cavities are plugged and lower portions of the cavities are filled essentially with air.

13. The radio frequency (RF) power transistor package as recited in claim 12 further including said die mount pedestal coupling to the first electrode interconnection on the first major side of a RF power transistor die wherein said die mount pedestal is coupled to an active area of the RF power transistor die to remove heat therefrom.

14. The radio frequency (RF) power transistor package as recited in claim 13 further including a second lead coupling to the second electrode interconnection on the second major surface of the RF power transistor die wherein said second lead is a thermal path for removing heat from the second major surface of the RF power transistor die.

15. The radio frequency (RF) power transistor package as recited in claim 12 wherein said surface of said die mount pedestal is smaller than the first major surface of the RF power transistor die.

16. The radio frequency (RF) power transistor package as recited in claim 15 further including a second isolation ring overlying said second major surface of said first isolation ring.

17. The radio frequency (RF) power transistor package as recited in claim 16 wherein a second lead couples through an opening in said second isolation ring to couple to the second electrode interconnection on the second major surface of the RF power transistor die.

18. The radio frequency (RF) power transistor package as recited in claim 17 wherein a third lead couples to an interconnect formed on said second major surface of said first isolation ring wherein said third lead is outside said second isolation ring.

19. The radio frequency (RF) power transistor package as recited in claim 18 wherein a portion of said second isolation ring underlies the RF power transistor die.

20. The radio frequency (RF) power transistor package as recited in claim 19 wherein the interconnect on the second major surface of the first isolation ring couples to the control electrode interconnection on the first major side of the RF power transistor die.

21. The radio frequency (RF) power transistor package as recited in claim 20 wherein solder is used to electrically and physically couple said first and second lead to the RF power transistor die.

22. The radio frequency (RF) power transistor package as recited in claim 20 wherein a conductive epoxy is used to electrically and physically couple said first and third lead to the RF power transistor die.

23. The radio frequency (RF) power transistor package as recited in claim 12, wherein the die mount pedestal is disposed in an opening of the first isolation ring.

24. A semiconductor package, comprising:

a semiconductor die having a first surface and a second surface opposite the first surface;

a first material; and

a second material different than the first material, wherein the first surface of the semiconductor die is coupled to the first and second materials and wherein the first surface of the semiconductor die overlies at least a portion of the first material and at least a portion of the second material;

wherein the semiconductor die further comprises a dielectric platform surrounding the active area and wherein a gate interconnection is over the dielectric platform to at least partially shield a gate electrode from a drain region of the semiconductor die, and further comprising a shielding plate being coupled to an external source lead of the semiconductor package via a source region of the semiconductor die and being disposed between the gate interconnection and the drain region to at least partially decouple the capacitance between the gate electrode and the drain region; and

wherein said dielectric platform comprises a matrix of silicon dioxide vertical structures and wherein the vertical structures are separated by cavities, top portions of the cavities are plugged and lower portions of the cavities are filled essentially with air.

25. The semiconductor package of claim 24, wherein the first material is coupled to the second material, wherein a first surface of the first material is substantially coplanar to a first surface of the second material, and wherein the first surface of the semiconductor die is coupled to the first surface of the first material and to the first surface of the second material.