Radio frequency power semiconductor device package comprising dielectric platform and shielding plate
First Claim
1. A radio frequency (RF) semiconductor device comprising:
- a die including an active area comprising an array of transistor cells, one or more of the transistor cells having a source region, a gate electrode and a drain region;
the drain regions of one or more of the transistor cells being coupled together, a metal gate interconnection on an upper surface of the die and coupled to the gate electrodes of the cells, a metal source interconnection on the upper surface of the die and coupled to the source regions of the cells, and a metal drain interconnection on a bottom surface of the die and coupled to the drain regions of the cells; and
a package to make electrical connections to the source regions, gate electrodes and drain regions of the cells, said package including an external source lead serving as a heat sink and coupled to the source interconnection, an external gate lead coupled to the gate interconnection, and an external drain lead coupled to the drain interconnection;
wherein the die further comprises a dielectric platform surrounding the active area and wherein the gate interconnection is over the dielectric platform to at least partially shield the gate electrode from the drain region of the die, and further comprising a shielding plate being coupled to the external source lead of the package via the source region and being disposed between the gate interconnection and the drain region to at least partially decouple the capacitance between the gate electrode and the drain region; and
wherein said dielectric platform comprises a matrix of silicon dioxide vertical structures and wherein the vertical structures are separated by cavities, top portions of the cavities are plugged and lower portions of the cavities are filled essentially with air.
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Accused Products
Abstract
A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.
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Citations
25 Claims
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1. A radio frequency (RF) semiconductor device comprising:
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a die including an active area comprising an array of transistor cells, one or more of the transistor cells having a source region, a gate electrode and a drain region; the drain regions of one or more of the transistor cells being coupled together, a metal gate interconnection on an upper surface of the die and coupled to the gate electrodes of the cells, a metal source interconnection on the upper surface of the die and coupled to the source regions of the cells, and a metal drain interconnection on a bottom surface of the die and coupled to the drain regions of the cells; and a package to make electrical connections to the source regions, gate electrodes and drain regions of the cells, said package including an external source lead serving as a heat sink and coupled to the source interconnection, an external gate lead coupled to the gate interconnection, and an external drain lead coupled to the drain interconnection; wherein the die further comprises a dielectric platform surrounding the active area and wherein the gate interconnection is over the dielectric platform to at least partially shield the gate electrode from the drain region of the die, and further comprising a shielding plate being coupled to the external source lead of the package via the source region and being disposed between the gate interconnection and the drain region to at least partially decouple the capacitance between the gate electrode and the drain region; and wherein said dielectric platform comprises a matrix of silicon dioxide vertical structures and wherein the vertical structures are separated by cavities, top portions of the cavities are plugged and lower portions of the cavities are filled essentially with air. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor package comprising:
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a semiconductor die; a first lead; a pedestal extending from a first surface of the first lead; and a non-conductive member adjacent the pedestal, wherein a first portion of the semiconductor die is coupled to a first portion of the pedestal and a second portion of the semiconductor die is coupled to a first portion of the non-conductive member; wherein the semiconductor die further comprises a dielectric platform surrounding an active area and wherein a gate interconnection is over the dielectric platform to at least partially shield a gate electrode from a drain region of the semiconductor die, and further comprising a shielding plate being coupled to an external source lead of the semiconductor package via a source region of the semiconductor die and being disposed between the gate interconnection and the drain region to at least partially decouple the capacitance between the gate electrode and the drain region; and wherein said dielectric platform comprises a matrix of silicon dioxide vertical structures and wherein the vertical structures are separated by cavities, top portions of the cavities are plugged and lower portions of the cavities are filled essentially with air. - View Dependent Claims (8, 9, 10, 11)
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12. A radio frequency (RF) power transistor package for housing a RF power transistor die having a first electrode interconnection and a control electrode interconnection on a first major surface of the die and a second electrode interconnection on a second major surface of the die, the RF power transistor package comprising:
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a first isolation ring having a first major surface and a second major surface; and a first lead coupled to said first major surface of said first isolation ring, said first lead having a die mount pedestal adjacent to said first isolation ring wherein a surface of said die mount pedestal is planar to or above said second major surface of said first isolation ring; wherein the die comprises a dielectric platform surrounding the active area and wherein a gate interconnection is over the dielectric platform to at least partially shield a gate electrode from a drain region of the die, and further comprising a shielding plate being coupled to an external source lead of the transistor package via a source region of the transistor die and being disposed between the gate interconnection and the drain region to at least partially decouple the capacitance between the gate electrode and the drain region; and wherein said dielectric platform comprises a matrix of silicon dioxide vertical structures and wherein the vertical structures are separated by cavities, top portions of the cavities are plugged and lower portions of the cavities are filled essentially with air. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A semiconductor package, comprising:
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a semiconductor die having a first surface and a second surface opposite the first surface; a first material; and a second material different than the first material, wherein the first surface of the semiconductor die is coupled to the first and second materials and wherein the first surface of the semiconductor die overlies at least a portion of the first material and at least a portion of the second material; wherein the semiconductor die further comprises a dielectric platform surrounding the active area and wherein a gate interconnection is over the dielectric platform to at least partially shield a gate electrode from a drain region of the semiconductor die, and further comprising a shielding plate being coupled to an external source lead of the semiconductor package via a source region of the semiconductor die and being disposed between the gate interconnection and the drain region to at least partially decouple the capacitance between the gate electrode and the drain region; and wherein said dielectric platform comprises a matrix of silicon dioxide vertical structures and wherein the vertical structures are separated by cavities, top portions of the cavities are plugged and lower portions of the cavities are filled essentially with air. - View Dependent Claims (25)
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Specification