Input termination for delay locked loop feedback with impedance matching
First Claim
1. A reference output circuit comprising:
- a control circuit that provides an output clock signal for driving one or more output signals from one or more corresponding output buffers, wherein the control circuit includes an output buffer circuit that provides a feedback clock signal in response to the output clock signal, and circuitry for generating the output clock signal in response to the feedback clock signal and an input clock signal, wherein the one or more output signals are synchronized with the input clock signal; and
a terminated load module coupled to receive the feedback clock signal, wherein the terminated load module switches between a pull-up configuration and a pull-down configuration in response to the output clock signal, wherein the terminated load module emulates terminated loads driven by the one or more output buffers.
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Accused Products
Abstract
A reference output circuit for generating an output clock signal for driving signals off of an integrated circuit chip uses a switched terminated load in combination with an output buffer to generate a feedback clock signal, which is used, in combination with a reference input clock signal, to generate the output clock signal. The switched terminated load uses transistors having the same size as transistors in the output buffer. The switched terminated load draws the same DC current as the output buffer. As a result, the switched terminated load and the output buffer have the same electro-migration performance. Pull-up and pull-down MOS impedances of the switched terminated load are easily adjusted during switching periods of the switched terminated load. The design of the switched terminated load minimizes variations in the terminated load impedance due to MOS impedance variations.
46 Citations
16 Claims
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1. A reference output circuit comprising:
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a control circuit that provides an output clock signal for driving one or more output signals from one or more corresponding output buffers, wherein the control circuit includes an output buffer circuit that provides a feedback clock signal in response to the output clock signal, and circuitry for generating the output clock signal in response to the feedback clock signal and an input clock signal, wherein the one or more output signals are synchronized with the input clock signal; and a terminated load module coupled to receive the feedback clock signal, wherein the terminated load module switches between a pull-up configuration and a pull-down configuration in response to the output clock signal, wherein the terminated load module emulates terminated loads driven by the one or more output buffers. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A reference output circuit comprising:
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a control circuit that provides an output clock signal for driving one or more output signals; and a terminated load module that switches between a pull-up configuration and a pull-down configuration in response to the output clock signal, wherein the terminated load module emulates terminated loads driven by the output signals, wherein the control circuit comprises circuitry for generating the output clock signal in response to a feedback clock signal and an input clock signal, the circuitry comprising; a first comparator coupled to receive the feedback clock signal and a reference voltage signal associated with a cross-over voltage of the feedback clock signal and the input clock signal; a second comparator coupled to receive the input clock signal and the reference voltage signal; and a delay locked loop circuit coupled to receive output signals from the first and second comparators, and in response, provide the output clock signal.
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8. A reference output circuit comprising:
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a control circuit that provides an output clock signal for driving one or more output signals from one or more corresponding output buffers, wherein the control circuit includes an output buffer circuit that provides a feedback clock signal in response to the output clock signal, wherein the output buffer circuit is configured to switch between a pull-up configuration and a pull-down configuration in response to the output clock signal; and a terminated load module coupled to receive the feedback clock signal, wherein the terminated load module switches between a pull-up configuration and a pull-down configuration in response to the output clock signal, wherein the terminated load module emulates terminated loads driven by the one or more output buffers; and a feedback path configured to receive the feedback clock signal from the output buffer circuit, wherein the feedback path includes a capacitor and the terminated load module.
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9. A reference output circuit comprising:
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a control circuit that provides an output clock signal for driving one or more output signals; and a terminated load module that switches between a pull-up configuration and a pull-down configuration in response to the output clock signal, wherein the terminated load module emulates terminated loads driven by the output signals, wherein the control circuit comprises circuitry for generating the output clock signal in response to a feedback clock signal and an input clock signal, the circuitry including an output buffer circuit configured to drive the feedback clock signal in response to the output clock signal, wherein the output buffer circuit is configured to switch between a pull-up configuration and a pull-down configuration, and a feedback path configured to receive the feedback clock signal from the output buffer circuit, wherein the feedback path includes a capacitor and the terminated load module, wherein the output buffer circuit includes a pull-up transistor and a pull-down transistor, which are commonly coupled to a signal line of the feedback path through a first resistor, and the terminated load module includes a pull-up transistor coupled to the signal line through a second resistor, and a pull-down transistor coupled to the signal line through a third resistor, wherein the second and third resistors each have a resistance which is greater than a resistance of the first resistor. - View Dependent Claims (10)
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11. A reference output circuit comprising:
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a control circuit that provides an output clock signal for driving one or more output signals; and a terminated load module that switches between a pull-up configuration and a pull-down configuration in response to the output clock signal, wherein the terminated load module emulates terminated loads driven by the output signals, wherein the control circuit comprises circuitry for generating the output clock signal in response to a feedback clock signal and an input clock signal, the circuitry including an output buffer circuit configured to drive the feedback clock signal in response to the output clock signal, wherein the output buffer circuit is configured to switch between a pull-up configuration and a pull-down configuration, and a feedback path configured to receive the feedback clock signal from the output buffer circuit, wherein the feedback path includes a capacitor and the terminated load module, wherein the output buffer circuit includes a pull-up transistor and a pull-down transistor, which are commonly coupled to a signal line of the feedback path through a first resistor, and the terminated load module includes a pull-up transistor and a pull-down transistor, which are commonly coupled to the signal line of the feedback path through a second resistor, wherein the second resistor has a resistance greater than a resistance of the first resistor. - View Dependent Claims (12)
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13. A method of driving signals off of an integrated circuit chip, the method comprising:
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generating an output clock signal; driving one or more signals off of the integrated circuit chip to one or more corresponding terminated loads in response to the output clock signal; switching a terminated load circuit on the integrated circuit chip in response to the output clock signal, wherein the terminated load circuit emulates the terminated loads located off of the integrated circuit chip; driving a feedback clock signal to a first logic state in response to a first transition of the output clock signal, wherein the feedback clock signal is driven to the first logic state by; turning on a pull-up transistor in an output buffer circuit; turning on a pull-up transistor in the terminated load circuit; turning off a pull-down transistor in the output buffer circuit; turning off a pull-down transistor in the terminated load circuit; and
thenturning off the pull-up transistor in the terminated load circuit and turning on the pull-down transistor in the terminated load circuit after the feedback clock signal has been driven to the first logic state. - View Dependent Claims (14, 15, 16)
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Specification