Operational time extension

• US 7,898,291 B2
• Filed: 08/03/2009
• Issued: 03/01/2011
• Est. Priority Date: 12/01/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Rohe, Andre, Teig, Steven, Schmit, Herman, Redgrave, Jason, Caldwell, Andrew
• Primary Examiner(s): Tan, Vibol
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US12/534,841
• Publication Number:
  US 20100066407A1
• Time in Patent Office: 575 Days
• Field of Search: 326 37- 41, 326/47, 716/2, 716/6, 716/10, 716/16
• US Class Current: 326/38
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration

Abstract

Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit. The method then maintains a configuration of the particular reconfigurable circuit constant over at least two contiguous reconfiguration cycles in order to reduce signal delay through the signal path and thereby satisfy the timing constraint.

Claims

1. An integrated circuit (“

IC”

) comprising;

a plurality of reconfigurable circuits that reconfigure a plurality of times in a plurality of configuration cycles, wherein a plurality of signals have to be maintained from a first configuration cycle to a second configuration cycle in order to satisfy a timing constraint of a reconfigurable circuit; and

a plurality of state elements for receiving said signals during the first configuration cycle, and storing said signals for circuits operating in the second configuration cycle, wherein at least one state element operates to pass a particular signal to a particular reconfigurable circuit in the first configuration cycle and operates to maintain the particular signal for the particular reconfigurable circuit in the second configuration cycle.

2. The IC of claim 1, wherein the state elements are latches that each includes an enable control, said enable control controllable by a voltage level of an enable signal received at the enable control.

3. The IC of claim 2, wherein the state elements are not registers.

4. The IC of claim 2, wherein each state element receives data and the enable signal, wherein the state element stores data that the state element receives when the enable signal is at a first voltage level and passes data that the state element receives when the enable signal is at a second voltage level.

5. The IC of claim 1, wherein the first and second configuration cycles are two successive configuration cycles.

6. The IC of claim 1, wherein the first and second configuration cycles are not two successive configuration cycles.

7. The IC of claim 1, wherein the first and second configuration cycles are sub-cycles of a design cycle of a user design implemented by the IC.

8. The IC of claim 1 further comprising a plurality of configurable logic circuits, wherein a plurality of maintained signals are signals computed by a plurality of configurable logic circuits in the first configuration cycle that are for computations performed by a plurality of configurable logic circuits in the second configuration cycle.

9. The IC of claim 8, wherein a plurality of the configurable logic circuits that produce or use the plurality of maintained signals are logic circuits that reconfigure between the first and second configuration cycles.

10. A method of mapping an integrated circuit (“

IC”

) design to an IC comprising a plurality of reconfigurable circuits performing a plurality of configurable operations in a plurality of configuration cycles, the method comprising;

identifying a signal path that uses a plurality of reconfigurable circuits in a plurality of configuration cycles in a manner that does not allow a signal to travel through at least a portion of the signal path within a desired time period;

identifying a location within the signal path for inserting a state element to allow the signal to travel through the portion of the signal path within the desired time period; and

defining a configuration data set to configure a first reconfigurable circuit to serve as the state element in first and second configuration cycles so that as the state element, the first reconfigurable circuit operates to pass a particular signal to a second reconfigurable circuit during the first configuration cycle and operates to maintain the particular signal for the second reconfigurable circuit in the second configuration cycle.

11. The method of claim 10, wherein the insertion of the state element is penalized in an optimizer for designing the IC.

12. The method of claim 10, wherein the second reconfigurable circuit is configured to perform a same operation in the first and second configuration cycles.

13. The method of claim 10, wherein the first and second configuration cycles are successive configuration cycles.

14. The method of claim 10, wherein the first and second configuration cycles are not successive configuration cycles.

15. An integrated circuit (“

IC”

) comprising;

a plurality of configurable circuits that operate in a plurality of operational cycles;

at least one signal path through a set of the configurable circuits, wherein a particular operation is assigned to a particular configurable circuit in both a first operational cycle and a second operational cycle so as to not violate a timing constraint for the signal path.

16. The IC of claim 15 further comprising a state element on the signal path to provide a same input to the particular configurable circuit in the first and second operational cycles.

17. The IC of claim 16, wherein the state element is configured to pass a particular signal to the particular configurable circuit in the first configuration cycle and hold the particular signal for the particular configurable circuit in the second configuration cycle.

18. The IC of claim 17, wherein the state element receives a control signal, wherein the state element passes the particular signal when the control signal is at a first level and the state element holds the particular signal when the control signal is at a second level.

19. The IC of claim 15, wherein the timing constraint is a requirement that all operations in a particular operational cycle be completed within a particular time duration.