Display drive integrated circuit and method for generating system clock signal
First Claim
Patent Images
1. A display drive integrated circuit for driving a display panel, comprising:
- a division rate output unit, comprising;
a counter which receives a dot clock signal and a horizontal synchronization signal from an external source via an interface, and which outputs a count value equaling a total number of clock cycles of the dot clock signal corresponding to one cycle of the horizontal synchronization signal, anda division rate output device which receives the count value and outputs a division rate value corresponding to an integer portion of a quotient obtained by dividing the count value by M where M is a natural number greater than one; and
a system clock generating unit which receives the dot clock signal and the division rate value and in response thereto generates a system clock signal by dividing a frequency of the dot clock signal by a divisor obtained by multiplying the division rate value by a fixed value.
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Abstract
A display drive integrated circuit is for driving a display panel. The display drive integrated circuit includes a division rate output unit which outputs as a division rate corresponding to a quotient obtained by dividing by M a total number of clock cycles of a dot clock signal corresponding to a clock cycle of a horizontal synchronization signal, where M is a natural number, and a system clock generating unit which generates a system clock signal by dividing the dot clock signal using the division rate.
43 Citations
18 Claims
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1. A display drive integrated circuit for driving a display panel, comprising:
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a division rate output unit, comprising; a counter which receives a dot clock signal and a horizontal synchronization signal from an external source via an interface, and which outputs a count value equaling a total number of clock cycles of the dot clock signal corresponding to one cycle of the horizontal synchronization signal, and a division rate output device which receives the count value and outputs a division rate value corresponding to an integer portion of a quotient obtained by dividing the count value by M where M is a natural number greater than one; and a system clock generating unit which receives the dot clock signal and the division rate value and in response thereto generates a system clock signal by dividing a frequency of the dot clock signal by a divisor obtained by multiplying the division rate value by a fixed value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of generating a system clock signal for a display drive integrated circuit which drives a display panel, the method comprising:
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receiving a dot clock signal and a horizontal synchronization signal from an external source via an interface; counting a number of cycles of the dot clock signal corresponding to one cycle of the horizontal synchronization signal and outputting a count value equaling a total number of clock cycles of the dot clock signal corresponding to one cycle of the horizontal synchronization signal; dividing the count value by M to produce a quotient, where M is a natural number; outputting a division rate value corresponding to an integer portion of the quotient; and generating the system clock signal by dividing a frequency of the dot clock signal by a divisor obtained by multiplying the division rate value by a fixed value. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification