Logical design of graphics system with reduced shadowed state memory requirements

• US 7,898,546 B1
• Filed: 11/03/2006
• Issued: 03/01/2011
• Est. Priority Date: 11/03/2006
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Montrym, John S., Eitzmann, Gregory M., Silkebakken, Richard A.
• Primary Examiner(s): Amini; Javid A
• Application Number:
  US11/556,646
• Time in Patent Office: 1,579 Days
• Field of Search: 345/522, 345/531, 345/543
• US Class Current: 345/522
• CPC Class Codes: G06T 1/60 Memory management

Abstract

A graphics processing unit is designed to have validation logic utilizing a reduced memory space shadow memory as a source of state information for performing validation of commands. A semantic analysis is performed to generate the validation logic such that the reduced memory space shadow memory has a size small than a memory size required to store a full representation of a set of state variables associated with a class of commands.

Claims

1. A system for designing a graphics processing system, comprising:

a class processor, said class processor receiving an abstract model of a graphics system having a class of commands and a set of state variables and in response performing semantic analysis to generate validation logic to validate commands within said class of commands, said validation logic configured to utilize a reduced memory space memory having a memory size smaller than a memory size associated with storing a full representation of said set of state variables, wherein said class processor is used to generate a database for creating a hardware description language representation of said validation logic and said reduced memory space shadow memory.

2. The system of claim 1, wherein said class processor receives a description of a graphics pipeline and generates a description of a front end command processor to map commands to instructions of said graphics pipeline, said validation logic and said reduced memory space memory disposed in said front-end command processor.

3. The system of claim 1, wherein said semantic analysis includes identifying redundant state variables not required to perform validity checks.

4. The system of claim 1, wherein said semantic analysis includes identifying translated forms of state variables having a reduced memory size requirement for use in performing validation.

5. The system of claim 1, wherein said class processor receives a first file describing said abstract model and a class of commands and also receives a second file having a description of a graphics pipeline.

6. A method of designing a graphics processing unit, comprising:

receiving an abstract model of a graphics system having a class of commands and a set of state variables; and

semantically processing said abstract model to generate validation logic for said class of commands utilizing a reduced memory space shadow memory having a memory size smaller than that of a memory size associated with storing a full representation of said set of state variables, wherein said semantic processing comprises semantic processing and parsing validation checks to determine a subset of said set of state variables required for validation.

7. The method of claim 6, wherein said semantic processing comprises generating a database for creating a hardware description language file to implement said validation logic in hardware.

8. The method of claim 6, wherein said semantic processing comprises semantic processing and parsing of validation checks to identify instances where translated versions of state variables may be used in validation to reduce shadow memory requirements.

9. The method of claim 6, wherein said semantic processing comprises semantic processing and parsing to organize validation checks to reduce shadow memory requirements.

10. The method of claim 6, wherein said semantic processing comprises determining a minimum shadow memory size to implement a validation of said class of commands.

11. The method of claim 6, further comprising implementing said validation logic in a front-end of a graphics processing unit.

12. The method of claim 6, wherein said semantic processing comprises:

receiving an engine tile defining attributes of a graphics pipeline;

receiving a master file defining said class of commands and said abstract model;

generating a front end having an interface for converting said class of commands into instructions for said graphics pipeline, said front-end including said validation logic and a reduced memory space shadow memory.

13. A computer program product comprising a non-transitory computer readable medium having computer code which when implemented on a computer implements a design of a graphics processing unit, comprising:

computer program code stored on said non-transitory computer readable medium for generating a front end to receive a class of commands belonging to an abstract machine representation having a set of state variables;

computer program code stored on said non-transitory computer readable medium for generating validation logic to validate input commands received by said front end; and

computer program code stored on said non-transitory computer readable medium for generating a reduced memory space shadow memory storing a representation of state information smaller in size than a full representation of said set of state variables,

said validation logic utilizing said reduced memory space shadow memory to provide state information for validation.

14. The non-transitory computer readable medium of claim 13, wherein said computer program code is stored on said non-transitory computer readable medium in a hardware description language.

15. The non-transitory computer readable medium of claim 13, wherein said reduced memory space shadow memory stores a subset of said set of state variables.

16. The non-transitory computer readable medium of claim 13, wherein said reduced memory space shadow memory stores a translated version of at least one state variable.