Electronic system and method for selectively allowing access to a shared memory
First Claim
1. A computing system comprising:
- a memory configured to store compressed image data in a compressed data buffer structure, the memory further configured to store intra-picture image data in a first image buffer and predicted-picture image data in a second image buffer;
a memory interface coupled to the memory and configured to arbitrate access to the memory;
a central processing unit (CPU) coupled to the memory interface and configured to direct operations of the computing system, the CPU sharing the memory with peripheral devices in the computing system;
a video controller configured to decode bidirectional image data and send the decoded bidirectional image data to a display adapter;
an encoder/decoder configured to share the memory, the encoder/decoder further configured retrieve compressed image data from the compressed data buffer structure and send intra-picture image data to the first image buffer and predicted-picture image data to the second image buffer;
the encoder/decoder further configured to send bidirectional image data to the video controller; and
a bus coupled to the memory interface, the encoder/decoder, and the video controller, the bus having sufficient capacity to operate as the only bus in the computing system configured to transfer data in real time between the memory, the encoder/decoder, and the video controller.
3 Assignments
0 Petitions
Accused Products
Abstract
An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.
-
Citations
10 Claims
-
1. A computing system comprising:
-
a memory configured to store compressed image data in a compressed data buffer structure, the memory further configured to store intra-picture image data in a first image buffer and predicted-picture image data in a second image buffer; a memory interface coupled to the memory and configured to arbitrate access to the memory; a central processing unit (CPU) coupled to the memory interface and configured to direct operations of the computing system, the CPU sharing the memory with peripheral devices in the computing system; a video controller configured to decode bidirectional image data and send the decoded bidirectional image data to a display adapter; an encoder/decoder configured to share the memory, the encoder/decoder further configured retrieve compressed image data from the compressed data buffer structure and send intra-picture image data to the first image buffer and predicted-picture image data to the second image buffer;
the encoder/decoder further configured to send bidirectional image data to the video controller; anda bus coupled to the memory interface, the encoder/decoder, and the video controller, the bus having sufficient capacity to operate as the only bus in the computing system configured to transfer data in real time between the memory, the encoder/decoder, and the video controller. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
Specification